71M6521BE
Energy Meter IC
DATA SHEET
JANUARY 2008
The CE program must begin on a 1Kbyte boundary of the flash address. The I/O RAM register CE_LCTN[4:0] defines which
1KB boundary contains the CE code. Thus, the first CE instruction is located at 1024*CE_LCTN[4:0].
The CE DRAM can be accessed by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time slots are re-
served for FIR, RTM, and MPU, respectively, to prevent bus contention for CE DRAM data access. Holding registers are used
to convert 8-bit wide MPU data to/from 32-bit wide CE DRAM data, and wait states are inserted as needed, depending on the
frequency of CKMPU.
The CE DRAM is 128 32-bit words. The MPU can read and write the CE DRAM as the primary means of data communication
between the two processors.
Table 2 shows the CE DRAM addresses allocated to analog inputs from the AFE.
Address (HEX)
Name
Description
Phase A current
Phase A voltage
Phase B current
(Phase B voltage – not used)
Not used
Not used
Temperature
Battery Voltage
00
01
02
03
04
05
06
07
IA
VA
IB
VB
-
-
TEMP
VBAT
Table 2: CE DRAM Locations for ADC Results
The CE of the 71M6521BE is aided by support hardware that facilitates implementation of equations, pulse counters, and
accumulators. This support hardware is controlled through I/O RAM locations EQU (equation assist), DIO_PV and DIO_PW
(pulse count assist), and PRE_SAMPS and SUM_CYCLES (accumulation assist). PRE_SAMPS and SUM_CYCLES support a dual
level accumulation scheme where the first accumulator accumulates results from PRE_SAMPS samples and the second accu-
mulator accumulates up to SUM_CYCLES of the first accumulator results. The integration time for each energy output is
PRE_SAMPS * SUM_CYCLES/2520.6 (with MUX_DIV = 1). CE hardware issues the XFER_BUSY interrupt when the
accumulation is complete.
Meter Equations
Compute Engine (CE) firmware for residential meter configurations implements the calculations for equation 0 for a single-
element, 2-wire, 1-phase meter with neutral current sense and tamper detection. The energy for element 0 is determined by
VA*IA, and the energy for element 1 is determined by VA*IB.
Real-Time Monitor
The CE contains a Real-Time Monitor (RTM), which can be programmed through the UART to monitor four selectable CE
DRAM locations at full sample rate. The four monitored locations are serially output to the TMUXOUT pin via the digital output
multiplexer at the beginning of each CE code pass. The RTM can be enabled and disabled with RTM_EN. The RTM output is
clocked by CKTEST. Each RTM word is clocked out in 35 cycles and contains a leading flag bit. See the Functional
Description section for the RTM output format. RTM is low when not in use.
Pulse Generator
The chip contains a pulse generator that creates low-jitter Wh pulses at a rate set by the CE.
The I/O RAM bit DIO_PW, as described in the Digital I/O section, can be programmed to route WPULSE to the output pin
DIO6. Pulses can also be output on OPT_TX (see OPT_TXE[1:0] for details).
The value of PLS_INTERVAL depends on the sample rate (nominal 2520Hz) and the number of times the pulse generator is
executed in the CE code. Changing these values would require redesign of all CE filters and/or modification of the CE pulse
generator code. Since these numbers are fixed for the CE code supplied by TERIDIAN, the value of PLS_INTERVAL is also
fixed, to a value of 0x81.
V1.0
© 2005-2008 TERIDIAN Semiconductor Corporation
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