71M6521BE
Energy Meter IC
DATA SHEET
JANUARY 2008
Port Registers: The I/O ports are controlled by Special Function Registers P0, P1, and P2. The contents of the SFR can be
observed on corresponding pins on the chip. Writing a ‘1’ to any of the ports (see Table 10) causes the corresponding pin to be
at high level (V3P3), and writing a ‘0’ causes the corresponding pin to be held at low level (GND). The data direction registers
DIR0, DIR1, and DIR2 define individual pins as input or output pins (see section Digital I/O for details).
SFR
Address
Register
P0
R/W Description
0x80
R/W Register for port 0 read and write operations (pins DIO4…DIO7)
DIR0
0xA2
R/W Data direction register for port 0. Setting a bit to 1 means that the corresponding pin is
an output.
P1
0x90
0x91
0xA0
0xA1
R/W Register for port 1 read and write operations (pins DIO8…DIO11, DIO14…DIO15)
R/W Data direction register for port 1.
DIR1
P2
R/W Register for port 2 read and write operations (pins DIO16…DIO17)
R/W Data direction register for port 2.
DIR2
Table 10: Port Registers
All DIO ports on the chip are bi-directional. Each of them consists of a Latch (SFR ‘P0’ to ‘P2’), an output driver, and an input
buffer, therefore the MPU can output or read data through any of these ports. Even if a DIO pin is configured as an output, the
state of the pin can still be read by the MPU, for example when counting pulses issued via DIO pins that are under
CE control.
The technique of reading the status of or generating interrupts based on DIO pins configured as outputs, can be
used to implement pulse counting.
Special Function Registers Specific to the 71M6521BE
Table 11 shows the location and description of the 71M6521BE-specific SFRs.
Register
ERASE
Alternative
Name
SFR
Address
R/W Description
FLSH_ERASE
0x94
W
This register is used to initiate either the Flash Mass Erase cycle or
the Flash Page Erase cycle. Specific patterns are expected for
FLSH_ERASE in order to initiate the appropriate Erase cycle (default =
0x00).
0x55 – Initiate Flash Page Erase cycle. Must be preceded by a write
to FLSH_PGADR @ SFR 0xB7.
0xAA – Initiate Flash Mass Erase cycle. Must be preceded by a write
to FLSH_MEEN @ SFR 0xB2 and the debug port must be
enabled.
Any other pattern written to FLSH_ERASE will have no effect.
PGADDR
FLSH_PGADR
0xB7
R/W
Flash Page Erase Address register containing the flash memory page
address (page 0 thru 127) that will be erased during the Page Erase
cycle (default = 0x00).
Must be re-written for each new Page Erase cycle.
EEDATA
EECTRL
0x9E
0x9F
R/W I2C EEPROM interface data register
I2C EEPROM interface control register. If the MPU wishes to write a
R/W
byte of data to EEPROM, it places the data in EEDATA and then
writes the ‘Transmit’ code to EECTRL. The write to EECTRL initiates
the transmit sequence. See the EEPROM Interface section for a
description of the command and status bits available for EECTRL.
V1.0
© 2005-2008 TERIDIAN Semiconductor Corporation
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