71M6515H
Energy Meter IC
DATA SHEET
MARCH 2008
Analog Pin Description
Name
IA,
IB,
IC
VA,
VB,
VC
VFLT
VX
VREF
XIN,
XOUT
Pin
No.
56
55
54
53
52
51
59
58
57
61
63
Type
I
I
I
I
I/O
I
Circuit
6
6
7
6
9
8
Description
Line Current Sense Inputs: Voltage inputs to the internal A/D converter. Typically,
they are connected to the output of a current transformer. The input is referenced
to V3P3A.
Unused pins must be tied to V3P3A.
Line Voltage Sense Inputs: Voltage inputs to the internal A/D converter. Typically,
they are connected to the output of a resistor divider. The input is referenced to
V3P3A.
Unused pins must be tied to V3P3A.
Power Fault Input.
This pin must be tied to V3P3A.
Auxiliary input (not used).
This pin should be tied to VREF.
Voltage Reference for the ADC.
Crystal Inputs: A 32768Hz crystal should be connected across these pins.
Typically, a 15pF capacitor is also connected from each pin to GNDA. See the
datasheet of the crystal manufacturer for details.
Pin types: P = Power, O = Output, I = Input, I/O = Input/Output
The circuit number denotes the equivalent circuit, as specified under “I/O Equivalent Circuits”.
Digital Pin Description
Unless otherwise indicated, all inputs and outputs are standard CMOS. Inputs do NOT have internal pull-ups or pull-downs.
Name
CKTEST
D0
D1
D2
D3
D4
D5
D6
D7
PULSE4
PULSE3
PULSE_INIT
BAUD_RATE
IRQZ
MUXSYNC
RESETZ
Pin
No.
6
42
21
22
23
37
38
39
33
15
14
40
16
41
25
47
Type
I/O
Circuit
4
Description
Clock PLL output. Can be enabled and disabled by
CKOUT_DSB
(see
Status Mask).
Input/output pins 0 through 7.
These pins must be terminated to
V3P3D or ground if configured as input pins.
D0 through D7 float after reset or power-up and are configured as
outputs and driven low 140ms after RESETZ goes high.
The fourth pulse generator output
The third pulse generator output
The pulse output initial power-up voltage (0: 0V, 1: 3.3V), default is 1.
This pin must be terminated to V3P3D or ground.
The UART baud rate (1: 38.4kbd, 0: 19.2kbd).
This pin must be
terminated to V3P3D or ground.
Interrupt output, low active. A falling edge indicates the end of a
measurement frame, as well as alarms. Rises when status word is read.
Internal signal. MUXSYNC falls at the beginning of each conversion
cycle (multiplexer frame).
Chip reset: Input pin with internal pull-up resistor, used to reset the chip
into a known state. For normal operation, this pin is set to 1. To reset
the chip, this pin is driven to 0 for 5 microseconds. No external reset
circuitry is necessary for power-up reset.
I/O
3, 4
O
O
I
I
O
O
I
4
4
3
3
4
4
1
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© 2005-2008 TERIDIAN Semiconductor Corporation
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