71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
AUGUST 2007
Refreshing the WD Timer: The watchdog timer must be refreshed regularly to prevent the reset request signal from becoming
active. This requirement imposes an obligation on the programmer to issue two instructions. The first instruction sets WDT and
the second instruction sets SWDT. The maximum delay allowed between setting WDT and SWDT is 12 clock cycles. If this
period has expired and SWDT has not been set, WDT is automatically reset, otherwise the watchdog timer is reloaded with the
content of the WDTREL register and WDT is automatically reset. Since the WDT requires exact timing, firmware needs to be
designed with special care in order to avoid unwanted WDT resets. TERIDIAN strongly discourages the use of the software
WDT.
Special Function Registers for the WD Timer
Interrupt Enable 0 Register (IEN0):
MSB
LSB
EX0
EAL
WDT
ET2
ES0
ET1
EX1
ET0
Table 26: The IEN0 Register (see also Table 34)
Bit
Symbol
WDT
Function
Watchdog timer refresh flag.
IEN0.6
Set to initiate a refresh of the watchdog timer. Must be set directly before SWDT
is set to prevent an unintentional refresh of the watchdog timer. WDT is reset by
hardware 12 clock cycles after it has been set.
Table 27: The IEN0 Bit Functions (see also Table 34)
Note: The remaining bits in the IEN0 register are not used for watchdog control
Interrupt Enable 1 Register (IEN1):
MSB
LSB
EXEN2
SWDT
EX6
EX5
EX4
EX3
EX2
Table 28: The IEN1 Register (see also Tables 35/36)
Bit
Symbol
SWDT
Function
Watchdog timer start/refresh flag.
IEN1.6
Set to activate/refresh the watchdog timer. When directly set after setting WDT, a
watchdog timer refresh is performed. Bit SWDT is reset by the hardware 12 clock
cycles after it has been set.
Table 29: The IEN1 Bit Functions (see also Tables 35/36)
Note: The remaining bits in the IEN1 register are not used for watchdog control
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