71M6403
Electronic Trip Unit
SEPTEMBER 2006
I/O RAM (Configuration RAM) – Alphabetical Order
Many functions of the chip can be controlled via the I/O RAM (Configuration RAM). The CE will also take some of its parameters
from the I/O RAM.
Bits with a W (write) direction are written by the MPU into I/O RAM. Typically, they are initially stored in flash memory and copied
to the I/O RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The
remaining bits are mapped to 2xxx. Bits with R (read) direction can only be read by the MPU. On power up, all bits are cleared
to zero unless otherwise stated. Generic SFR registers are not listed.
Location
Name
Dir
Description
[Bit(s)]
2005[3]
2000[4]
2002[5:4]
ADC_DIS
CE_EN
CHOP_EN[1:0]
R/W Disables ADC and removes bias current
R/W CE enable.
R/W Chop enable for the reference band gap circuit.
00: enabled 01: disabled 10: disabled 11: enabled
R/W Must be 0.
RESERVED
2004[5]
COMP_INT[1:0]
2003[4:3]
R/W Two bits establishing whether a comparator state change should
create MPU interrupts. 1: interrupt, 0: no interrupt. If 11, the
comparator outputs are XOR’ed.
Bit0 = comp2, Bit1 = comp3
COMP_STAT[2:0]
2003[2:0]
R
Three bits containing comparator output status.
Bit0 = comp1, Bit1 = comp2, Bit2 = comp3
DIO_R0[2:0]
DIO_R1[2:0]
DIO_R2[2:0]
DIO_R3[2:0]
DIO_R4[2:0]
DIO_R5[2:0]
DIO_R6[2:0]
DIO_R7[2:0]
DIO_R8[2:0]
DIO_R9[2:0]
DIO_R10[2:0]
DIO_R11[2:0]
2009[2:0]
2009[6:4]
200A[2:0]
200A[6:4]
200B[2:0]
200B[6:4]
200C[2:0]
200C[6:4]
200D[2:0]
200D[6:4]
200E[2:0]
200E[6:4]
R/W Connects dedicated I/O pins 0 to 11 to selectable internal resources. If
R/W more than one input is connected to the same resource, the ‘Multiple’
R/W column below specifies how they are combined. See Software User’s
R/W Guide for details).
R/W
DIO_GP
Resource
Multiple
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
2
3
4
5
6
7
NONE
--
Reserved
OR
OR
OR
OR
OR
OR
OR
T0 (counter0 clock)
T1 (counter1 clock)
High priority I/O interrupt (int0 rising)
Low priority I/O interrupt (int1 rising)
High priority I/O interrupt (int0 falling)
Low priority I/O interrupt (int1 falling)
DIO_DIR0[7:0]
SFR A2
R/W Programs the direction of DIO pins 7 through 0. 1 indicates output.
Ignored if the pin is not configured as I/O. See DIO_EEX for special
option for DIO4 and DIO5.
DIO_DIR1[7:0]
DIO_DIR2[5:0]
SFR 91
R/W Programs the direction of DIO pins 15 through 8. 1 indicates output.
Ignored if the pin is not configured as I/O.
R/W Programs the direction of DIO pins 21 through 16. 1 indicates output.
Ignored if the pin is not configured as I/O.
SFR A1[5:0]
Page: 52 of 75
© 2006 TERIDIAN Semiconductor Corporation
REV 1.0
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
