71M6403
Electronic Trip Unit
SEPTEMBER 2006
HARDWARE DESCRIPTION
Hardware Overview
The TERIDIAN 71M6403 single chip Electronic Trip Unit integrates all primary functional blocks required to implement a solid-
state circuit breaker. Included on chip are an analog front end (AFE), an 8051-compatible microprocessor (MPU) which executes
one instruction per clock cycle (80515), an independent 32-bit digital computation engine (CE), a voltage reference, LCD drivers,
RAM, FLASH memory, and a variety of I/O pins. Various current sensor technologies are supported including Current
Transformers (CT), Resistive Shunts, and Rogowski (di/dt) Coils.
Measurements can be displayed on either a 3V or a 5V LCD. Flexible mapping of LCD display segments will facilitate integration
with any LCD format. The design trade-off between the number of LCD segments and DIO pins can be flexibly configured using
memory-mapped I/O to accommodate various requirements.
The 71M6403 includes several I/O peripheral functions that improve the functionality of the device and reduce the component
count for most circuit breaker applications. The I/O peripherals include two UARTs, digital I/O, comparator inputs, LCD display
drivers, I
2
C interface and an optical/IR interface.
One of the two internal UARTs (UART1) is adapted to support an Infrared LED with higher internal drive output and sense input.
It can also be configured to function as a standard UART with normal digital IOs.
A block diagram of the chip is shown in Figure 1. A detailed description of various hardware blocks follows.
External Components
The 71M6403 is optimized for fast startup. To achieve this, an external 19.6608 MHz oscillator is required to drive CK, the
primary clock input. The frequency for the CK38 input is generated from the 19.6608 MHz oscillator using an inexpensive
‘HC4040 counter chip. The divide-by-512 output of the ‘HC4040 generates a 38.4 kHz signal.
Analog Front End (AFE)
The AFE of the TERIDIAN 71M6403 Electronic Trip Unit IC is comprised of an input multiplexer, a delta-sigma A/D converter
with internal voltage reference, followed by an FIR filter. A block diagram of the AFE is shown in Figure 3.
Multiplexer
The input multiplexer supports eight input signals that are applied to the pins I0 through I5, INEUTRAL plus the output of the
internal temperature sensor. The multiplexer can be operated in two modes:
•
•
During a normal multiplexer cycle, the signals from the six pins I0 through I5 are selected.
During the alternate multiplexer cycle, the temperature signal (TEMP) , INEUTRAL, and I1, I3, I4, I5 (EQU = 101) signal
sources are selected. Use of the alternate multiplexer cycle is not recommended for fast response circuit breaker
applications. Upon enabling the alternate multiplexer cycle, the I0 and I2 current samples are interrupted delaying over
current trip detection response time.
Regular multiplexer sequence
Mux State:
0
I0
1
I1
2
I2
3
I3
4
I4
5
I5
Alternate multiplexer sequence
Mux State:
0
TEMP
1
I1
2
INEUTRAL
3
I3
4
I4
5
I5
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles (EQU = 101)
Note: Use of the alternate multiplexer cycle is not recommend.
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2006 TERIDIAN Semiconductor Corporation
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