71M6403
Electronic Trip Unit
SEPTEMBER 2006
RTM Probes:
RTM0[7:0]
RTM0
RTM1
RTM2
RTM3
2060
2061
2062
2063
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
Synchronous Serial Interface:
SSI_EN
SSI_10M
SSI_CKGATE
SSI_FSIZE[1:0]
SSI_BEG[7:0]
SSI_END[7:0]
SSI_FPOL
SSI_RDYEN SSI_RDYPOL
SSI
2070
S S I _B E G 2071
SSI_END 2072
Fuse Selection Registers:
TRIMSEL[7:0]
TRIMSEL 20FD
TRIM
TRIM[7:0]
20FF
SFR MAP (SFRs Specific to TERIDIAN 80515) – In Numerical Order
‘Not Used’ bits are blacked out and contain no memory and are read by the MPU as zero. RESERVED bits are in use and
should not be changed. This table lists only the SFR registers that are not generic 8051 SFR registers.
SFR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr
Digital I/O:
DIO_0[7:0]
DIO_DIR0[7:0]
DIO_1[7:0]
DIO_DIR1[7:0]
DIO_2[5:0]
(Port 0)
P0
DIR0
P1
80
A2
90
91
A0
A1
(Port 1)
(Port 2)
DIR1
P2
DIO_DIR2[5:0]
DIR2
Interrupts and WD Timer:
INT6
INT5
INT4
INT3
INT2
INT1
IE_ZP8
INT0
IE_XFER
INTBITS
WDI
F8
E8
WD_RST
Flash:
FLSH_ERASE[7:0]
ERASE
94
PREBOOT
SECURE
FLSH_MEEN FLSH_PWE
FLSHCTL B2
FLSH_PGADR[6:0]
PGADR
B7
Serial EEPROM:
EEDATA[7:0]
EECTRL[7:0]
EEDATA
EECTRL
9E
9F
Page: 51 of 75
© 2006 TERIDIAN Semiconductor Corporation
REV 1.0
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
