71M6403
Electronic Trip Unit
SEPTEMBER 2006
Figure 10, Figure 11, and Figure 12 show the RTM and SSI timing, respectively.
PLLOUT
CK32
MUX_SYNC
CK/4
0
1
30 31
0
1
30 31
0
1
30 31
0
1
30 31
TMUXOUT/RTM
FLAG
FLAG
FLAG
FLAG
RTMDATA0 (32 bits)
RTMDATA1 (32 bits)
RTMDATA2 (32 bits)
RTMDATA3 (32 bits)
Figure 10: RTM Output Format
If SSI_CKGATE =1
If 16bit fields
If 32bit fields
If SSI_CKGATE =1
SFR (Output)
SRDY (Input)
SCLK (Output)
SSDATA (Output)
31 30
16 15
1
0
31 30
16 15
1
0
31
1
0
SSI_BEG
SSI_BEG+1
SSI_END
MUX_SYNC
Figure 11: SSI Timing, (SSI_FPOL = SSI_RDYPOL = 0)
Next field is delayed while SRDY is low
SFR (Output)
SRDY (Input)
SCLK (Output)
SSDATA (Output)
31 30 29
18 17 16 16 16 16 15 14 13 12
Figure 12: SSI Timing, 16-bit Field Example (External Device Delays SRDY)
SFR is the framing pulse. Although CE words are always 32 bits, the SSI interface will frame the entire data block as a single
field, as multiple 16-bit fields, or as multiple 32-bit fields. The SFR pulse is one SCLK clock cycle wide, changes state on the
rising edge of SCLK and precedes the first bit of each field.
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© 2006 TERIDIAN Semiconductor Corporation
REV 1.0
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