U842B
VBatt
R1
180 Ω
R9
220 kΩ
8
6
5
7
C1
47 µF
C2
100 nF
R7
1.5 kΩ
U842B
1
2
3
4
R6
R4
10 kΩ
10 kΩ
R11
R5
360 Ω
47 kΩ
Switch
INT
VR1
1 kΩ
Button
WASH
13288
PARK
Figure 3. Basic cicuitry
threshold of the oscillator. For all other time periods, an
internal voltage divider determines the upper charging
threshold of the oscillator (see figure 2).
Variable Debouncing Times
Debouncing is basically done by counting oscillator
clocks starting with the occurance of any input signal.
Timing
Caused by the asynchronism of input signal and IC-clock,
the debouncing time may vary in a certain range.
Fixed:
Relay activation time
Dry wiping
t
t
=
=
160 1/f
896 1/f
or 3 cycles
5
0
0
Figure 4 shows the short circuit debouncing as an
example:
2
During the relay activation, a comparator monitors the
output current at each positive edge of the clock to load
a 3-stage shift register in the case of a detected short cir-
cuit condition i.e., I > 500 mA. With the third edge, the
output stage is disabled. Dependent on the short circuit
occurence the delay time may range from 2 to 3 clock
cycles.
Interval pause
t
t
=
=
872 1/f
6
0
Switch-on delay INT
Variable:
8 1/f
0
4D
Debouncing time INT
Debouncing time WASH
1. pre-wash delay
t
4
=
24 to 32 1/f
0
t
t
t
t
=
=
=
=
112 to 128 1/f
1
0
The timing can be adjusted by variation of the external
frequency-determining components (R/C).
2. reverse debouncing
Debouncing time PARK
Debouncing time SC
16 to 32 1/f
1.R
8
0
6 to 8 1/f
2 to 3 1/f
0
0
The potentiometer at Pin 4 determines the interval pause,
which can be varied by adjusting the upper charging
7
TELEFUNKEN Semiconductors
3 (12)
Rev. A2, 03-Feb-97
TEMIC [ TEMIC SEMICONDUCTORS ]
