TSC87C52
VCC
VCC
ICC
VCC
ICC
VCC
VCC
VCC
P0
P0
VCC
RST
EA
RST
EA
XTAL2
XTAL1
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
(NC)
VSS
VSS
All other pins are disconnected.
All other pins are disconnected.
Figure 12 ICC Test Condition, Power Down Mode
Figure 10 ICC Test Condition, Active Mode
VCC
ICC
VCC
VCC
VCC–0.5V
0.7VCC
P0
0.2VCC–0.1
0.45V
TCLCH
TCHCL
RST
EA
TCLCH = TCHCL = 5ns.
XTAL2
XTAL1
(NC)
CLOCK
SIGNAL
VSS
All other pins are disconnected.
Figure 13 Clock Signal Waveform for ICC Tests in
Active and Idle Modes
Figure 11 ICC Test Condition, Idle Mode
MATRA MHS
Rev. C – 10 Sept 1997
17
Preliminary