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TSC87C52-16CJB 参数 Datasheet PDF下载

TSC87C52-16CJB图片预览
型号: TSC87C52-16CJB
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS 0至33 MHz的可编程的8位微控制器 [CMOS 0 to 33 MHz Programmable 8?bit Microcontroller]
分类和应用: 微控制器
文件页数/大小: 24 页 / 184 K
品牌: TEMIC [ TEMIC SEMICONDUCTORS ]
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TSC87C52  
CMOS 0 to 33 MHz Programmable 8–bit Microcontroller  
Description  
TEMIC’s TSC87C52 is high performance CMOS  
EPROM version of the 80C52 CMOS single chip 8 bit  
microcontroller.  
structure; a full duplex serial port with framing error  
detection; a power off flag; and an on-chip oscillator.  
The TSC87C52 has 2 software-selectable modes of  
reduced activity for further reduction in power  
consumption. In the idle mode the CPU is frozen while  
the RAM, the timers, the serial port and the interrupt  
system continue to function. In the power down mode  
the RAM is saved and all other functions are inoperative.  
The fully static design of the TSC87C52 allows to  
reduce system power consumption by bringing the clock  
frequency down to any value, even DC, without loss of  
data.  
The TSC87C52 is manufactured using non volatile  
SCMOS process which allows it to run up to:  
The TSC87C52 retains all the features of the 80C52 with  
some enhancement: 8 K bytes of internal code memory  
(EPROM); 256 bytes of internal data memory (RAM);  
32 I/O lines; three 16 bit timers one with count–down  
and clock–out capability; a 6-source, 2-level interrupt  
D
D
33 MHz with VCC = 5 V ± 10%.  
16 MHz with 2.7 V < VCC < 5.5 V.  
Features  
D
8 Kbytes of EPROM  
D
D
D
D
D
Fully static design  
G
Improved Quick Pulse programming algorithm  
Secret ROM by encryption  
0.8µ SCMOS non volatile process  
ONCE Mode  
G
D
D
D
D
D
256 bytes of RAM  
Enhanced Hooks system for emulation purpose  
Available temperature ranges:  
64 Kbytes program memory space  
64 Kbytes data memory space  
32 programmable I/O lines  
G
commercial  
industrial  
G
Three 16 bit timer/counters including enhanced  
timer 2  
D
Available packages:  
G
PDIP40 (OTP)  
D
Programmable serial port with framing error  
detection  
G
G
G
G
PLCC44 (OTP)  
PQFP44 (OTP)  
D
D
Power control modes  
CQPJ44 (UV erasable)  
CERDIP40 (UV erasable)  
Two–level interrupt priority  
MATRA MHS  
Rev. C – 10 Sept 1997  
1
Preliminary