TSC80251G2D
5.2 Signals
Table 2. Product Name Signal Descriptions
Signal
Name
Alternate
Function
Type
Description
th
A17
O
18 Address Bit
P1.7
Output to memory as 18th external address bit (A17) in extended bus applications, depending
on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13, Page 15).
th
A16
O
17 Address Bit
Output to memory as 17th external address bit (A16) in extended bus applications, depending
on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13, Page 15).
P3.7
(1)
A15:8
O
I/O
O
Address Lines
P2.7:0
P0.7:0
Upper address lines for the external bus.
(1)
AD7:0
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
ALE
Address Latch Enable
ALE signals the start of an external bus cycle and indicates that valid address information
are available on lines A16/A17 and A7:0. An external latch can use ALE to demultiplex the
address from address/data bus.
AWAIT#
I
Real-time Asynchronous Wait States Input
When this pin is active (low level), the memory cycle is stretched until it becomes high.
When using the Product Name as a pin-for-pin replacement for a 8xC51 product, AWAIT#
can be unconnected without loss of compatibility or power consumption increase (on-chip
pull-up).
Not available on DIP package.
CEX4:0
EA#
I/O
I
PCA Input/Output pins
P1.7:3
CEXx are input signals for the PCA capture mode and output signals for the PCA compare
and PWM modes.
External Access Enable
EA# directs program memory accesses to on-chip or off-chip code memory.
For EA#= 0, all program memory accesses are off-chip.
For EA#= 1, an access is on-chip ROM if the address is within the range of the on-chip
ROM; otherwise the access is off-chip. The value of EA# is latched at reset.
For devices without ROM on-chip, EA# must be strapped to ground.
ECI
O
PCA External Clock input
P1.2
P1.5
ECI is the external clock input to the 16-bit PCA timer.
MISO
I/O
SPI Master Input Slave Output line
When SPI is in master mode, MISO receives data from the slave peripheral. When SPI is in
slave mode, MISO outputs data to the master controller.
MOSI
I/O
I
SPI Master Output Slave Input line
P1.7
When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in
slave mode, MOSI receives data from the master controller.
INT1:0#
External Interrupts 0 and 1
P3.3:2
INT1#/INT0# inputs set IE1:0 in the TCON register. If bits IT1:0 in the TCON register are
set, bits IE1:0 are set by a falling edge on INT1#/INT0#. If bits IT1:0 are cleared, bits IE1:0
are set by a low level on INT1#/INT0#.
NMI
I
Non Maskable Interrupt
Holding this pin high for 24 oscillator periods triggers an interrupt.
When using the Product Name as a pin-for-pin replacement for a 8xC51 product, NMI can
be unconnected without loss of compatibility or power consumption increase (on-chip pull-
down).
Not available on DIP package.
P0.0:7
I/O
Port 0
AD7:0
P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float
and can be used as high impedance inputs. To avoid any paraitic current consumption, Floating
P0 inputs must be polarized to V or V
.
SS
DD
6
Rev. A - May 7, 1999
TEMIC [ TEMIC SEMICONDUCTORS ]
