TSC80251G2D
ALE
(1)
T
LHLL
(1)
(1)
RLRH
T
T
T
RHLH2
LLRL
RD#/PSEN#
(1)
RLDV
T
T
RLAZ
(1)
T
T
LHAX
RHDZ2
(1)
T
T
T
RHDX
AVLL
LLAX
P2
A15:8
D7:0
(1)
Data In
T
AVRL
(1)
T
T
AVDV1
(1)
RHAX
T
AVDV2
P0/A16/A17
A7:0/A16/A17
Note:
1. The value of this parameter depends on wait states. See Table 45 and Table 46.
Figure 20. External Bus Cycle: Data Read (Page Mode)
ALE
WR#
(1)
T
LHLL
(1)
T
T
WLWH
WHLH
(1)
T
LHAX
T
QVWH
(1)
T
T
T
AVLL
LLAX
WHQX
P2
A15:8
D7:0
(1)
Data Out
T
AVWL1
(1)
T
T
AVWL2
WHAX
P0/A16/A17
A7:0/A16/A17
Note:
1. The value of this parameter depends on wait states. See Table 45 and Table 46.
Figure 21. External Bus Cycle: Data Write (Page Mode)
44
Rev. A - May 7, 1999