TSC80251G2D
Table 32. Summary of Conditional Jump Instructions (2/2)
Jump if bit
JB <src>, rel
(PC) ← (PC) + size (instr);
IF [src opnd= 1] THEN (PC) ← (PC) + rel
(PC) ← (PC) + size (instr);
IF [src opnd= 0] THEN (PC) ← (PC) + rel
(PC) ← (PC) + size (instr);
Jump if not bit
Jump if bit and clear
JNB <src>, rel
JBC <dest>, rel
IF [dest opnd= 1] THEN
dest opnd ← 0
(PC) ← (PC) + rel
Jump if accumulator is zero
Jump if accumulator is not zero
Compare and jump if not equal
JZ rel
(PC) ← (PC) + size (instr);
IF [(A)= 0] THEN (PC) ← (PC) + rel
(PC) ← (PC) + size (instr);
IF [(A) ≠ 0] THEN (PC) ← (PC) + rel
(PC) ← (PC) + size (instr);
JNZ rel
CJNE <src1>, <src2>, rel
IF [src opnd1 < src opnd2] THEN (CY) ← 1
IF [src opnd1 ≥ src opnd2] THEN (CY) ← 0
IF [src opnd1 ≠ src opnd2] THEN (PC) ← (PC) + rel
(PC) ← (PC) + size (instr); dest opnd ← dest opnd -1;
IF [ϕ (Z)] THEN (PC) ← (PC) + rel
Decrement and jump if not zero
DJNZ <dest>, rel
Binary Mode(2) Source Mode(2)
Mnemonic
<dest>, <src>(1)
Comments
Bytes States Bytes States
(3)(6)
(3)(6)
(3)(6)
(3)(6)
(5)(6)
(5)(6)
(3)(6)
(3)(6)
(3)(6)
(3)
bit51, rel
bit, rel
Jump if direct bit is set
3
5
3
5
3
5
2
2
3
3
3
3
2
3
2/5
4/7
2/5
4/7
4/7
3
4
3
4
3
4
2
2
3
3
4
4
3
3
2/5
3/6
2/5
JB
Jump if direct bit of 8-bit address location is set
Jump if direct bit is not set
bit51, rel
bit, rel
JNB
JBC
Jump if direct bit of 8-bit address location is not set
Jump if direct bit is set & clear bit
3/6
(5)(6)
(5)(6)
(6)
bit51, rel
bit, rel
4/7
6/9
Jump if direct bit of 8-bit address location is set and clear
Jump if ACC is zero
7/10
2/5
(6)
(6)
JZ
rel
2/5
(6)
JNZ
rel
Jump if ACC is not zero
2/5
2/5
(3)(6)
(6)
(3)(6)
(6)
A, dir8, rel
A, #data, rel
Rn, #data, rel
@Ri, #data, rel
Rn, rel
Compare direct address to ACC and jump if not equal
Compare immediate to ACC and jump if not equal
Compare immediate to register and jump if not equal
Compare immediate to indirect and jump if not equal
Decrement register and jump if not zero
Decrement direct address and jump if not zero
2/5
2/5
2/5
2/5
CJNE
(6)
(6)
(6)
(6)
(6)
(6)
2/5
3/6
3/6
2/5
4/7
3/6
DJNZ
(4)(6)
(4)(6)
dir8, rel
3/6
3/6
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. States are given as jump not-taken/taken.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
5. If this instruction addresses an I/O Port (Px, x= 0-3), add 3 to the number of states. Add 5 if it addresses a Peripheral SFR.
6. In internal execution only, add 1 to the number of states of the ‘jump taken’ if the destination address is internal and odd.
Rev. A - May 7, 1999
26
TEMIC [ TEMIC SEMICONDUCTORS ]
