TS80C52X2
10.3 DC Parameters for Low Voltage
TA = 0°C to +70°C; V = 0 V; V = 2.7 V to 5.5 V ± 10%; F = 0 to 30 MHz.
SS
CC
TA = -40°C to +85°C; V = 0 V; V = 2.7 V to 5.5 V ± 10%; F = 0 to 30 MHz.
SS
CC
Table 23. DC Parameters for Low Voltage
Symbol
Parameter
Min
Typ
Max
Unit
V
Test Conditions
V
Input Low Voltage
-0.5
0.2 V - 0.1
CC
IL
V
Input High Voltage except XTAL1, RST
Input High Voltage, XTAL1, RST
0.2 V + 0.9
V
V
+ 0.5
+ 0.5
V
IH
CC
CC
CC
V
0.7 V
V
IH1
CC
(6)
(4)
V
0.45
V
OL
Output Low Voltage, ports 1, 2, 3
I
= 0.8 mA
OL
(6)
(4)
V
0.45
V
OL1
Output Low Voltage, port 0, ALE, PSEN
Output High Voltage, ports 1, 2, 3
Output High Voltage, port 0, ALE, PSEN
Logical 0 Input Current ports 1, 2 and 3
Input Leakage Current
I
I
I
= 1.6 mA
= -10 µA
= -40 µA
OL
OH
OH
V
0.9 V
0.9 V
V
OH
CC
CC
V
V
OH1
I
-50
±10
-650
200
10
µA
µA
µA
kΩ
pF
Vin = 0.45 V
IL
LI
I
0.45 V < Vin < V
Vin = 2.0 V
CC
I
Logical 1 to 0 Transition Current, ports 1, 2, 3
RST Pulldown Resistor
TL
RST
(5)
R
50
90
CIO
Capacitance of I/O Buffer
Fc = 1 MHz
TA = 25°C
(5)
(3)
I
Power Down Current
TBD
µA
PD
TBD
V
= 2.0 V to 5.5 V
CC
(7)
I
CC
Power Supply Current
(5)
(5)
(1)
(2)
TBD
TBD
mA
mA
Active Mode 16MHz
Idle Mode 16MHz
TBD
TBD
V
V
= 3.3 V
= 3.3 V
CC
CC
NOTES
1. Operating I is measured with all output pins disconnected; XTAL1 driven with T
, T
= 5 ns (see Figure 16.), V = V + 0.5 V,
IL SS
CC
CLCH CHCL
V
= V - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = V . I would be slightly higher if a crystal oscillator used..
CC CC CC
IH
2. Idle I is measured with all output pins disconnected; XTAL1 driven with T
, T
= 5 ns, V = V + 0.5 V, V = V - 0.5 V; XTAL2
CC
CLCH CHCL IL SS IH CC
N.C; Port 0 = V ; EA = RST = V (see Figure 14.).
CC
SS
3. Power Down I is measured with all output pins disconnected; EA = V , PORT 0 = V ; XTAL2 NC.; RST = V (see Figure 15.).
CC
SS
CC
SS
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V s of ALE and Ports 1 and 3. The noise is
OL
due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst
cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi V peak 0.6V. A Schmitt Trigger use is not necessary.
OL
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V.
6. Under steady state (non-transient) conditions, I must be externally limited as follows:
OL
Maximum I per port pin: 10 mA
OL
Maximum I per 8-bit port:
OL
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total I for all output pins: 71 mA
OL
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
OL
OL
7. For other values, please contact your sales office.
Rev. B - Jan. 25, 1999
41
Preliminary
TEMIC [ TEMIC SEMICONDUCTORS ]
