80C32/80C52
Serial Port Timing – Shift Register Mode (values in ns)
16 MHz 20 MHz 25 MHz 30 MHz 36 MHz 40 MHz 42 MHz 44 MHz
min max min max min max min max min max min max min max min max
SYM-
BOL
PARAMETER
TXLXL Serial Port Clock Cycle Time
750
563
600
480
480
380
400
300
330
220
250
170
230
150
227
140
TQVXH Output Data Setup to Clock
Rising Edge
TXHQX Output Data Hold after Clock
Rising Edge
63
0
90
0
65
0
50
0
45
0
35
0
30
0
25
0
TXHDX Input Data Hold after Clock
Rising Edge
TXHDV Clock Rising Edge to Input
Data Valid
563
450
350
300
250
200
180
160
Shift Register Timing Waveforms
MATRA MHS
17
Rev. G (14 Jan. 97)