L 67201/L 67202
MATRA MHS
Figure 7. Output Load.
AC Test Conditions
3.3 V
Input pulse levels
Input rise/Fall times
Input timing reference levels
Output reference levels
Output load
: Gnd to 3.0 V
600 Ω
: 5 ns
TO
OUTPUT
PIN
: 1.5 V
: 1.5 V
: See figure 7
30 pF*
780 Ω
* includes jig and scope capacitance
L 67201/202
– 55
L 67201/202
– 60
L 67201/202
– 65
SYMBOL
(16)
SYMBOL
(17)
PARAMETER (18) (22)
UNIT
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
READ CYCLE
TRLRL
tRC
Read cycle time
70
–
–
55
–
75
–
–
60
–
80
–
–
65
–
ns
ns
ns
ns
ns
ns
ns
ns
TRLQV
tA
Access time
TRHRL
tRR
Read recovery time
15
55
10
15
5
15
60
–
15
65
10
15
5
TRLRH
tRPW
tRLZ
tWLZ
tDV
Read pulse width (19)
Read low to data low Z (20)
Write low to data low Z (20, 21)
Data valid from read high
Read high to data high Z (20)
–
–
–
TRLQX
–
–
–
TWHQX
TRHQX
TRHQZ
–
–
–
–
–
5
–
–
tRHZ
–
30
–
–
–
30
WRITE CYCLE
TWLWL
TWLWH
TWHWL
TDVWH
TWHDX
tWC
Write cycle time
Write pulse width (19)
Write recovery time
Data set-up time
Data hold time
70
55
15
30
5
–
–
–
–
–
75
60
15
30
5
–
–
–
–
–
80
65
15
30
10
–
–
–
–
–
ns
ns
ns
ns
ns
tWPW
tWR
tDS
tDH
RESET CYCLE
TRSLWL
TRSLRSH
TWHRSH
TRSHWL
tRSC
Reset cycle time
70
55
55
15
–
–
–
–
75
60
60
15
–
–
–
–
80
65
65
15
–
–
–
–
ns
ns
ns
ns
tRS
Reset pulse width (19)
Reset set-up time
tRSS
tRSR
Reset recovery time
RETRANSMIT CYCLE
TRTLWL
TRTLRTH
TWHRTH
TRTHWL
FLAGS
tRTC
tRT
Retransmit cycle time
70
55
55
15
–
–
–
–
75
60
60
15
–
–
–
–
80
65
65
15
–
–
–
–
ns
ns
ns
ns
Retransmit pulse width (19)
Retransmit set-up time (20)
Retransmit recovery time
tRTS
tRTR
TRSLEFL
TRSLFFH
TRLEFL
TRHFFH
TEFHRH
TWHEFH
TWLFFL
TWLHFL
TRHHFH
tEFL
Reset to EF low
–
–
65
65
50
50
–
–
–
75
75
55
55
–
–
–
75
75
60
60
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHFH, tFFH
tREF
Reset to HF/FF high
Read low to EF low
Read high to FF high
Read width after EF high
Write high to EF high
Write low to FF low
Write low to HF low
Read high to HF high
–
–
–
tRFF
–
–
–
tRPE
55
–
60
–
65
–
tWEF
tWFF
tWHF
tRHF
50
50
65
65
55
55
75
75
60
60
75
75
–
–
–
–
–
–
–
–
–
10
Rev. C (10/11/95)