80C154/83C154
D If C/T = 0, the WATCHDOG is a TIMER that is D As there are no precautions for protecting bit WDT
incremented every machine cycle. If C/T = 1, the
WATCHDOG is a counter that is incremented by an
external signal of which the frequency cannot exceed
OSC ÷ 24.
from spurious writing in the IOCON register, special
care must be taken when writing the program. In
particular, the user should use the IOCON register bit
handling instructions :
–
SETB and CLR x
D The overflow of the TIMER/COUNTER is signalled
by raising flag TF1 to 1. The reset of the 83C154 is
executed during the next machine cycle and lasts for
the next 5 machine cycles. The results of this reset are
identical to those of a hardware reset. The internal
RAM is not affected and the special register assume
the values shown in Table 3.
in preference to the byte handling instructions :
MOV IOCON, # XXH, ORL IOCON, #XXH,
ANL IOCON, #XXH
–
–
External Counting in Power-down Mode
(PD = PCON.1 = 1)
Table 3. Content of the SFRS after a reset triggered
by the watchdog.
D In the power-down mode, the oscillator is turned off
and the 83C154’s activity is frozen. However, if an
external clock is connected to one of the two inputs,
T1/T0, TIMER/COUNTERS 0 and 1 can continue to
operate.
REGISTER
CONTENT
PC
ACC
B
000H
00H
00H
In this case, counting becomes asychronous and the
maximum, admissible frequency of the signal is
OSC : 24.
PSW
SP
00H
07H
DPTR
P0-P3
IP
0000H
0FFH
0X000000B
0X000000B
00H
D The overflow of either counter TF0 or TF1 causes an
interrupt to be serviced or forces a reset if the counter
is in the WATCHDOG MODE (T32 = ICON.7 = 1).
IE
TMOD
TCON
T2CON
TH0
00H
00H
00H
TL0
00H
TH1
00H
TL1
00H
TH2
00H
TL2
00H
RCAP2H
RCAP2L
SCON
SBUF
IOCON
PCON
00H
00H
00H
Indeterminate
00H
000X0000B
12
MATRA MHS
Rev.F (14 Jan. 97)
TEMIC [ TEMIC SEMICONDUCTORS ]
