80C154/83C154
32 Bit Counter
Figure 13 illustrates the 32 bit COUNTER mode.
Figure 12. 32 Bit Counter Configuration.
D In this mode, T32 = 0 and C/T0 = 1. Before it can
make an increment, the 83C154µ must detect two
transitions on its T0 input. As shown in figure 14,
input T0 is sampled on each S5P2 state of every
machine cycle or, in other words, every OSC ÷ 12.
Figure 13. Counter Incrementation Condition.
D The counter will only evolve if a level 1 is detected
during state S5P2 of cycle Ci and if a level 0 is
detected during state S5P2 of cycle Ci + n.
Figure 14. The Different Watchdog Configurations.
D Consequently, the minimal period of signal fEXT
admissible by the counter must be greater than or
equal to two machine cycles. The following formula
should be used to calculate the operating frequency.
fEXT
(
65536ć T0, Ă T1
f +
)
OSC
24
fEXT t
Watchdog Mode
D WDT = 1 enables access to this mode. As shown in
figure 15, all the modes of TIMERS 0 and 1, of which
the overflows act on TF1 (TF1 = 1), activate the
WATCHDOG Mode.
MATRA MHS
11
Rev.F (14 Jan. 97)
TEMIC [ TEMIC SEMICONDUCTORS ]
