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AD80C154-20D 参数 Datasheet PDF下载

AD80C154-20D图片预览
型号: AD80C154-20D
PDF下载: 下载PDF文件 查看货源
内容描述: [暂无描述]
分类和应用: 微控制器外围集成电路异步传输模式ATM时钟
文件页数/大小: 24 页 / 242 K
品牌: TEMIC [ TEMIC SEMICONDUCTORS ]
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80C154/83C154  
ALE  
XTAL1  
Address Latch Enable output for latching the low byte of  
the address during accesses to external memory. ALE is  
activated as though for this purpose at a constant rate of  
1/6 the oscillator frequency except during an external  
data memory access at which time one ALE pulse is  
skipped. ALE can sink or source 8 LS TTL inputs. It can  
drive CMOS inputs without an external pullup.  
Input to the inverting amplifier that forms the oscillator.  
Receives the external oscillator signal when an external  
oscillator is used.  
XTAL2  
Output of the inverting amplifier that forms the oscillator,  
and input to the internal clock generator. This pin should  
be floated when an external oscillator is used.  
PSEN  
Program Store Enable output is the read strobe to external  
Program Memory. PSEN is activated twice each machine  
cycle during fetches from external Program Memory.  
(However, when executing out of external Program  
Memory, two activations of PSEN are skipped during  
each access to external Data Memory). PSEN is not  
activated during fetches from internal Program Memory.  
PSEN can sink/source 8 LS TTL inputs. It can drive  
CMOS inputs without an external pullup.  
EA  
When EA is held high, the CPU executed out of internal  
Program Memory (unless the Program Counter exceeds  
3FFFH). When EA is held low, the CPU executes only out  
of external Program Memory. EA must not be floated.  
Idle and Power Down Operation  
Figure 3 shows the internal Idle and Power Down clock  
configuration. As illustrated, Power Down operation  
stops the oscillator. The interrupt, serial port, and timer  
blocks continue to function only with external clock  
(INT0, INT1, T0, T1).  
Idle Mode operation allows the interrupt, serial port, and  
timer blocks to continue to function with internal or  
external clocks, while the clock to CPU is gated off. The  
special modes are activated by software via the Special  
Function Register, PCON. Its hardware address is 87H.  
PCON is not bit addressable.  
Figure 3. Idle and Power Down Hardware.  
MATRA MHS  
5
Rev.F (14 Jan. 97)  
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