欢迎访问ic37.com |
会员登录 免费注册
发布采购

A4K-L67142V-55 参数 Datasheet PDF下载

A4K-L67142V-55图片预览
型号: A4K-L67142V-55
PDF下载: 下载PDF文件 查看货源
内容描述: [Dual-Port SRAM, 2KX8, 55ns, CMOS, LCC-48]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 14 页 / 178 K
品牌: TEMIC [ TEMIC SEMICONDUCTORS ]
 浏览型号A4K-L67142V-55的Datasheet PDF文件第6页浏览型号A4K-L67142V-55的Datasheet PDF文件第7页浏览型号A4K-L67142V-55的Datasheet PDF文件第8页浏览型号A4K-L67142V-55的Datasheet PDF文件第9页浏览型号A4K-L67142V-55的Datasheet PDF文件第10页浏览型号A4K-L67142V-55的Datasheet PDF文件第12页浏览型号A4K-L67142V-55的Datasheet PDF文件第13页浏览型号A4K-L67142V-55的Datasheet PDF文件第14页  
L67132/L67142  
Timing Waveform of Read with BUSY (46, 47, 48) (For L 67132)  
Notes : 46. To ensure that the earlier of the two port wins.  
47. Write cycle parameters should be adhered to, to ensure proper writing.  
48. Device is continuously enabled for both ports.  
49. OE at L for the reading port.  
Timing Waveform of Write with Port-to-port (50, 51, 52) (For L 67142 only)  
Notes : 50. Assume BUSY = H for the writing port, and OE = L for the reading port.  
51. Write cycle parameters should be adhered to, to ensure proper writing.  
52. Device is continuously enabled for both ports.  
MATRA MHS  
11  
Rev. D (19 Fev. 97)