MATRA MHS
single word to be read after one word has been written to
an empty FIFO stack. The data is enabled on the bus at
(tWEF + tA) ns after the leading edge of W which is
known as the first write edge and remains on the bus until
the R line is raised from low to high, after which the bus
will go into a three-state mode after tRHZ ns. The EF line
will show a pulse indicating temporary reset and then will
be set. In the interval in which R is low, more words may
be written to the FIFO stack (the subsequent writes after
the first write edge will reset the Empty Flag) ; however,
the same word (written on the first write edge) presented
to the output bus as the read pointer will not be
incremented if R is low. On toggling R, the remaining
words written to the FIFO will appear on the output bus
in accordance with the read cycle timings.
L 67201/L 67202
In the write flow-through mode (figure 18), the FIFO
stack allows a single word of data to be written
immediately after a single word of data has been read
from a full FIFO stack. The R line causes the FF to be
reset, but the W line, being low, causes it to be set again
in anticipation of a new data word. The new word is
loaded into the FIFO stack on the leading edge of W. The
W line must be toggled when FF is not set in order to write
new data into the FIFO stack and to increment the write
pointer.
Figure 4. Block Diagram of 1536
×
9 / 3072
×
9 FIFO Memory (Depth expansion).
XO
W
6
9
FF
9
EF
L
67201/202
FL
9
Q
V
CC
R
FULL
FF
9
L
67201/202
EF
EMPTY
FL
FF
9
RS
EF
L
67201/202
FL
XI
Figure 5. Compound FIFO Expansion.
Q
0
– Q
8
Q
0
– Q
8
R . W . RS
L 67201/202
DEPTH
EXPANSION
BLOCK
Q
9
– Q
17
Q
9
– Q
17
L 67201/202
DEPTH
EXPANSION
BLOCK
L 67201/202
DEPTH
EXPANSION
BLOCK
Q
(N–8)
– Q
N
Q
(N–8)
– Q
N
I
0
– I
8
I
0
– I
8
I
9
– I
17
I
9
– I
17
I
(N–8)
– I
N
I
(N–8)
– I
N
Notes :
6. For depth expansion block see section on Depth Expansion and Figure 4.
7. For Flag detection see section on Width Expansion and Figure 3.
Rev. C (10/11/95)
7
TEMIC [ TEMIC SEMICONDUCTORS ]
