L67132/L67142
Truth Table
(4)
Table 1 : Non Contention Read/Write Control
LEFT OR RIGHT PORT(1)
FUNCTION
R/W
X
CS
H
OE
X
D0–7
Z
Port Disabled and in Power Down Mode. ICCSB or ICCSB1
(2)
L
L
X
DATA
Data on Port Written into memory
IN
(3)
H
L
L
DATA
Z
Data in Memory Output on Port
OUT
H
L
H
High Impedance Outputs
Notes : 1. A – A
≠ A – A
.
OL
10L
0R
10R
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see t
and t
DDD
timing.
WDD
4. H = HIGH, L = LOW, X = DON’T CARE, Z = HIGH IMPEDANCE.
(5)
Table 2 : Arbitration
LEFT PORT
RIGHT PORT
FLAGS
BUSYL
FUNCTION
CSL
H
A0L – A10L
CSR
A0L – A10R
BUSYR
X
Any
X
H
H
L
L
X
X
H
H
H
H
H
H
H
H
No Contention
L
No Contention
No Contention
No Contention
H
Any
L
≠ A – A
≠ A – A
0L 10L
0R
10R
ADDRESS ARBITRATION WITH CE LOW BEFORE ADDRESS MATCH
L
L
L
L
LV5R
RV5L
Same
Same
L
L
L
L
LV5R
RV5L
Same
Same
H
L
H
L
L
H
L
L–Port Wins
R–Port Wins
Arbitration Resolved
Arbitration Resolved
H
CS ARBITRATION WITH ADDRESS MATCH BEFORE CS
LL5R
RL5L
LW5R
LW5R
= A – A
LL5R
RL5L
LW5R
LW5R
= A – A
10L
H
L
H
L
L
H
L
L–Port Wins
0R
10R
10R
0L
= A – A
= A
A
R–Port Wins
0R
0L – 10L
= A
A
= A – A
Arbitration Resolved
Arbitration Resolved
0R – 10R
0L
10L
= A – A
= A – A
H
0R
10R
0L
10L
Notes : 5. X = DON’T CARE, L = LOW, H = HIGH.
LV5R = Left Address Valid ≥ 5 ns before right address.
RV5L = Right address Valid ≥ 5 ns before left address.
Same = Left and Right Addresses match within 5 ns of each other.
LL5R = Left CS = LOW ≥ 5 ns before Right CS.
RL5L = Right CS = LOW ≥ 5 ns before left CS.
LW5R = Left and Right CS = LOW within 5 ns of each other.
4
MATRA MHS
Rev. D (19 Fev. 97)
TEMIC [ TEMIC SEMICONDUCTORS ]
