L67130/L67140
Data Bus Width Expansion
Master/Slave Description
Expanding the data bus width to 16 or more bits in a
dual-port RAM system means that several chips may be
active simultaneously. If every chip has a hardware
arbitrator, and the addresses for each chip arrive at the
same time one chip may activate its L BUSY signal while
another activates its R BUSY signal. Both sides are now
busy and the CPUs will wait indefinitely for their port to
become free.
To overcome this “Busy Lock-Out” problem, MHS has
developed a MASTER/SLAVE system which uses a
single hardware arbitrator located on the MASTER. The
SLAVE has BUSY inputs which allow direct interface to
the MASTER with no external components, giving a
speed advantage over other systems.
When dual-port RAMs are expanded in width, the
SLAVE RAMs must be prevented from writing until the
BUSY input has been settled. Otherwise, the SLAVE chip
may begin a write cycle during a conflict situation. On the
opposite, the write pulse must extend a hold time beyond
BUSY to ensure that a write cycle occurs once the conflict
is resolved. This timing is inherent in all dual-port
memory systems where more than one chip is active at the
same time.
The write pulse to the SLAVE must be inhibited by the
MASTER’s maximum arbitration time. If a conflict then
occurs, the write to the SLAVE will be inhibited because
of the MASTER’s BUSY signal.
Truth Table
Table 1 : Non Contention Read/Write Control
(4)
LEFT OR RIGHT PORT
(1)
FUNCTION
R/W
X
L
H
H
Notes :
CS
H
L
L
L
OE
X
X
L
H
D0–7
Z
DATA
IN
DATA
OUT
Z
Port Disabled and in Power Down Mode. ICCSB or ICCSB1
Data on Port Written into memory
(2)
Data in Memory Output on Port
(3)
High Impedance Outputs
1. A
0L
– A
10L
≠
A
0R
– A
10R
.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see t
WDD
and t
DDD
timing.
4. H = HIGH, L = LOW, X = DON’T CARE, Z = HIGH IMPEDANCE.
4
MATRA MHS
Rev. D (19 Fev. 97)
TEMIC [ TEMIC SEMICONDUCTORS ]
