80C32/80C52
MATRA MHS
External Data Memory Characteristics (values in ns)
16 MHz 20 MHz 25 MHz 30 MHz 36 MHz 40 MHz 42 MHz 44 MHz
min max min max min max min max min max min max min max min max
SYM-
BOL
PARAMETER
TRLRH RD pulse Width
340
340
85
270
270
85
210
210
70
180
180
55
120
120
35
100
100
30
90
90
25
80
80
25
TWLWH WR pulse Width
TLLAX Address Hold After ALE
TRLDV RD to Valid in
240
210
175
135
110
90
80
70
TRHDX Data hold after RD
TRHDZ Data float after RD
TLLDV ALE to Valid Data In
TAVDV Address to Valid Data IN
TLLWL ALE to WR or RD
0
0
0
0
0
0
0
0
90
90
80
70
50
45
150
180
95
40
140
175
90
35
130
170
85
435
480
370
400
350
300
235
260
170
190
150 250 135 170 120 130 90 115 70 100 60
55
60
8
50
55
6
TAVWL Address to WR or RD
TQVWX Data valid to WR transition
TQVWH Data Setup to WR transition
TWHQX Data Hold after WR
TRLAZ RD low to Address Float
TWHLH RD or WR high to ALE high
180
35
180
35
140
30
115
20
75
15
65
10
380
40
325
35
250
30
215
20
170
15
160
10
150
8
140
6
0
0
0
0
0
0
0
0
35
90
35
60
25
45
20
40
20
40
15
35
13
33
13
33
External Data Memory Write Cycle
External Data Memory Read Cycle
16
Rev. E (31/08/95)
TEMIC [ TEMIC SEMICONDUCTORS ]
