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5962-8753101TX 参数 Datasheet PDF下载

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型号: 5962-8753101TX
PDF下载: 下载PDF文件 查看货源
内容描述: [FIFO, 512X9, 30ns, Asynchronous, CMOS, CDIP28, CERAMIC, DIP-28]
分类和应用: 先进先出芯片
文件页数/大小: 17 页 / 131 K
品牌: TEMIC [ TEMIC SEMICONDUCTORS ]
 浏览型号5962-8753101TX的Datasheet PDF文件第2页浏览型号5962-8753101TX的Datasheet PDF文件第3页浏览型号5962-8753101TX的Datasheet PDF文件第4页浏览型号5962-8753101TX的Datasheet PDF文件第5页浏览型号5962-8753101TX的Datasheet PDF文件第7页浏览型号5962-8753101TX的Datasheet PDF文件第8页浏览型号5962-8753101TX的Datasheet PDF文件第9页浏览型号5962-8753101TX的Datasheet PDF文件第10页  
TABLE I. Electrical performance characteristics.
Test
|
|Symbol
|
|
|
|
|t
RC
|
|
|t
A
|
|
|t
RR
|
|
|t
RPW
|
|
|t
RLZ
4/
|
|
|t
WLZ
4/
|
|
|t
DV
|
|
|t
RHZ
4/
|
|
|t
WC
|
|
|t
WPW
|
|
|t
WR
|
|
|t
DS
|
|
|t
DH
|
|
|t
RSC
|
|
|t
RS
|
|
|t
RSR
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
Conditions 2/ 3/
-55
G
C < T
C
< +125
G
C
V
SS
= 0 V
4.5 V < V
CC
< 5.5 V
unless otherwise specified
|
|
|Group
A
|Device
|subgroups |
types
|
|
|
|
|
|
01
|9,
10, 11
|
02
|
03
|
|
|
01
|9,
10, 11
|
02
|
03
|
|
|
01
|9,
10, 11
|
02
|
03
|
|
|
01
|9,
10, 11
|
02
|
03
|
|
|
|9,
10, 11
|
All
|
|
|
|
|9,
10, 11
|
All
|
|
|
|
|9,
10, 11
|
All
|
|
|
|
|9,
10, 11
|
01
|
|
02,03
|
|
01
|9,
10, 11
|
02
|
03
|
|
|
01
|9,
10, 11
|
02
|
03
|
|
|
01
|9,
10, 11
|
02
|
03
|
|
|
01
|9,
10, 11
|
02
|
03
|
|
|
01
|9,
10, 11
|
02
|
03
|
|
|
01
|9,
10, 11
|
02
|
03
|
|
|
01
|9,
10, 11
|
02
|
03
|
|
|
01
|9,
10, 11
|
02
|
|
03
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Limits
|
|
|
Max
|
|
|
|
30
|
50
|
80
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
20
|
30
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Unit
|
|
|
|
|
ns
|
|
|
ns
|
|
|
ns
|
|
|
ns
|
|
|
ns
|
|
|
ns
|
|
|
ns
|
|
|
ns
|
|
|
ns
|
|
|
ns
|
|
|
ns
|
|
|
ns
|
|
|
ns
|
|
|
ns
|
|
|
ns
|
|
|
ns
|
Read cycle time
Access time
Read recovery time
Read pulse width
Read pulse low to data
bus at low-Z
Write pulse low to data
bus at low-Z
Data valid from read
pulse high
Read pulse high to data
bus at high-Z
Write cycle time
Write pulse width
Write recovery time
Data setup time
Data hold time
Reset cycle time
Reset pulse width
Reset recovery time
Min
40
65
100
10
15
20
30
50
80
5
5
5
40
65
100
30
50
80
10
15
20
18
30
40
0
5
10
40
65
100
30
50
80
10
15
20
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
C
5962-87531
SHEET
6