4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
TC7129
measurement of the time to ramp the integrated voltage to
zero, and is therefore proportional to the input voltage being
measured. This count can then be scaled and displayed as
a measurement of the input voltage. Figure 9 shows the
phases of the dual-slope conversion.
The dual-slope method has a fundamental limitation.
The count can only stop on a clock cycle, so that measure-
ment accuracy is limited to the clock frequency. In addition,
a delay in the zero-crossing comparator can add to the
inaccuracy. Figure 10 shows these errors in an actual
measurement.
RC Oscillator
For applications in which 3-1/2 digit (100 µV) resolution
is sufficient, an RC oscillator is adequate. A recommended
value for the capacitor is 51 pF. Other values can be used as
long as they are sufficiently larger than the circuit parasitic
capacitance. The resistor value is calculated from:
0.45
R =
freq
C
*
For 120 kHz frequency and C = 51 pF, the calculated
value of R is 75 kΩ. The RC oscillator and the crystal
oscillator circuits are shown in Figure 8.
DEINTEGRATE
INTEGRATE
Measuring Techniques
Two important techniques are used in the TC7129:
successive integration and digital auto-zeroing. Successive
integration is a refinement to the traditional dual-slope
conversion technique.
ZERO
CROSSING
Dual-Slope Conversion
TIME
A dual-slope conversion has two basic phases: inte-
grate and deintegrate. During the integrate phase, the input
signal is integrated for a fixed period of time; the integrated
voltage level is thus proportional to the input voltage. During
the deintegrate phase, the integrated voltage is ramped
down at a fixed slope, and a counter counts the clock cycles
until the integrator voltage crosses zero. The count is a
Figure 9. Dual-Slope Conversion
Successive Integration
The successive integration technique picks up where
dual-slope conversion ends. The overshoot voltage shown
in Figure 10, called the "integrator residue voltage," is
measuredtoobtainacorrectiontotheinitialcount. Figure11
shows the cycles in a successive integration measurement.
The waveform shown is for a negative input signal. The
sequence of events during the measurement cycle is:
Phase
Description
TC7129
1
40
2
INT1
Input signal is integrated for fixed time. (1000 clock
cycles on 2V scale, 10,000 on 200 mV)
270 kΩ
DE1
Integrator voltage is ramped to zero. Counter counts
up until zero crossing to produce reading accurate
to 3-1/2 digits. Residue represents an overshoot of
the actual input voltage.
5 pF
10 pF
120 kHz
+
+
V
V
REST
X10
Rest; circuit settles.
Residue voltage is amplified 10 times and inverted.
DE2
Integrator voltage is ramped to zero. Counter counts
down until zero crossing to correct reading to 4-1/2
digits. Residue represents an undershoot of the
actual input voltage.
TC7129
1
40
2
REST
X10
Rest; circuit settles.
75 kΩ
Residue voltage is amplified 10 times and inverted.
51 pF
DE3
Integrator voltage is ramped to zero. Counter counts
up until zero crossing to correct reading to 5-1/2
digits. Residue is discarded.
Figure 8. Oscillator Circuits
3-240
TELCOM SEMICONDUCTOR, INC.
TELCOM [ TELCOM SEMICONDUCTOR, INC ]
