PRECISION ANALOG FRONT ENDS
TC500
TC500A
TC510
TC514
is that, during the initial stage of input integration when the
integratorvoltageislow, thecomparatormaybeaffectedby
noise and its output unreliable. Once integration is well
underway, the comparator will be in a defined state.
Integrator Output Zero phase
The comparator delay and the controller's response
latency may result in Overshoot causing charge buildup on
the integrator at the end of a conversion. This charge must
be removed or performance will degrade. The Integrator
Output Zero phase should be activated (AB = 00) until
CMPTR goes high. It is absolutely critical that this phase be
terminated immediately so that Overshoot is not allowed to
occur in the opposite direction. At this point, it can be
assured that the integrator is near zero. Auto Zero should be
entered (AB = 01) and the TC5xx held in this state until the
next cycle is begun.
Reference Deintegration
The length of this phase must be precisely measured
from the transition of AB from 10 to 11 to the falling edge of
CMPTR. The comparator delay contributes some error in
timing this phase. The typical delay is specified to be 2µsec.
This should be considered in the context of the length of a
single count when determining overall system performance
and possible single-count errors. Additionally, Overshoot
will result in charge accumulating on the integrator after its
output crosses zero. This charge must be nulled during the
Integrator Output Zero phase.
TIME
AUTO -ZERO
CONVERTER
STATUS
INTEGRATE
FULL SCALE INPUT
REFERENCE
DEINTEGRATE
OVERSHOOT INTEGRATOR
OUTPUT
ZERO
INTEGRATOR
VOLTAGE
0
INT
V
COMPARATOR DELAY
UNDEFINED
0 FOR NEGATIVE INPUT
1 FOR POSITIVE INPUT
COMPARATOR
OUTPUT
A
A = 1
B = 1
A = 1
B = 0
A = 0
B = 1
A = 0
B = 0
AB INPUTS
B
READY FOR NEXT
CONVERSION
(AUTO-ZERO IS IDLE
STATE)
I
NTEGRATOR
CAPTURE
DEINTEGRATION
TIME
TIME INPUT
INTEGRATION
PHASE
BEGIN CONVERSION
WITH AUTO-ZERO PHASE
CONTROLLER
OPERATION
OUTPUT
ZERO PHASE
COMPLETE
SAMPLE INPUT POLARITY
t
TYPICALLY = t
INT
INT
MINIMIZING OVERSHOOT
WILL MINIMIZE I.O.Z. TIME
COMPARATOR DELAY +
PROCESSOR LATENCY
(POSITIVE INPUT SHOWN)
The length of this phase
is chosen almost arbitrarily
but needs to be long enough
to null out worst case errors
(see text)
NOTES
Figure 8. Typical Dual Slope A/D Converter System Timing
3-30
TELCOM SEMICONDUCTOR, INC.
TELCOM [ TELCOM SEMICONDUCTOR, INC ]
