ECONOMONITOR™ – 3-PIN SYSTEM SUPERVISOR
WITH POWER SUPPLY MONITOR AND WATCHDOG
TC32M
DETAILED DESCRIPTION
The TC32M provides three important functions to safe-
guard stable processor operation: precision processor moni-
tor, watchdog sanity timer and external override reset
control.
so the time between toggles is less than one watchdog
timeout period. The strobe signal can be derived from
microprocessor address, data and/or control signals. Typi-
cal circuit examples are shown in Figure 4.
Resistor Value Selection
The values of R1 and R2 must be chosen to ensure a
valid low strobe level (V
STL
) on RS when the processor I/O
line is low. The use of 10kΩ,
±5%
tolerance resistors are
recommended. These values result in a nominal strobe level
of 2.5 on RS (min/max of 2.13V / 3.08V, assuming V
DD
=
5.0V
±10%).
Other resistor values can be used, so long as
the additive tolerances of the power supply and resistor
values result in a strobe that falls within V
STH
and V
STL
under
all additive tolerance conditions.
Processor Monitor
The RS pin is immediately driven low any time V
DD
is
below the nominal threshold voltage. As a result, this pin is
LOW when power is initially applied, holding the processor
in its reset state. RS remains low for a minimum of 500msec
after V
DD
is within tolerance to allow the power supply and
processor to stabilize.
Watchdog Timer
The processor drives the RS pin with an input/output
(I/O) line in series with an resistor voltage divider to V
DD.
Pulling the bottom resistor of this divider low results in an
internal voltage change (strobe) sufficient to reset the watch-
dog timer, but above the V
IL
input threshold of the processor
RESET pin. The processor must continuously apply strobes
in this manner within a set period to verify proper software
execution. A momentary reset (500msec minimum) is gen-
erated by the TC32M if a hardware or software failure keeps
RS from being strobed within the watchdog timeout period.
This action typically initiates the processor's power-up rou-
tine. If the interruption persists, new reset pulses are gener-
ated each timeout period until RS is strobed. This timeout
period is typically 700msec.
The software routine that drives the RS strobe must be
in a section of the program that executes frequently enough
External Override Reset Control
A built-in debounce circuit allows a push-button switch
(PB) or other electronic signal to be wire-ORed to this pin as
an external RESET override control. The external
RESET is required to be an active low signal. Internally, this
input is timed to provide a minimum RESET pulse width of
500msec. Reference Figure 2.
Supply Monitor Noise Sensitivity
The TC32M is optimized for fast response to negative-
going changes in V
DD
. Systems with an inordinate amount
of electrical noise on V
DD
(such as systems using relays),
may require a 0.01µF bypass capacitor to reduce detection
sensitivity. This capacitor should be installed as close to the
TC32M as possible to keep the capacitor lead length short.
5V
5V
R1, 10k
R2,10k
MICRO-
CONTROLLER
R1, 10k
R2, 10k
DECODER
MICRO-
PROCESSOR
PO.1
RS
TC32M
ADDRESS
RS
TC32M
RESET
RESET
RESET
RESET
MICROCONTROLLER EXAMPLE
MICROPROCESSOR EXAMPLE
Figure 4. TC32M Hardware Connections (R1, R2 chosen to Meet V
STH
, V
STL
)
5-6
TELCOM SEMICONDUCTOR, INC.
TELCOM [ TELCOM SEMICONDUCTOR, INC ]
