3-1/2 DIGIT A/D CONVERTERS
TC14433
TC14433A
PIN DESCRIPTIONS
(Cont.)
Pin No. Pin No.
24-Pin
24-Pin
PDIP/CerDip SOIC
16
17
18
19
20
21
22
23
24
16
17
18
19
20
21
22
23
24
1
Pin No.
28-Pin
PLCC
19
20
21
23
24
25
26
28
28
8,15, 22
2
Symbol
DS
4
DS
3
DS
2
DS
1
Q
0
Q
1
Q
2
Q
3
V
DD
NC
Description
Digit select pins — The digit select output goes high when the respective digit
is selected. The MSD (1/2 digit) turns on immediately after an EOC pulse.
The remaining digits turn on in sequence from MSD to LSD.
To ensure that the BCD data has settled, an inter-digit blanking time of two
clock periods is included.
Clock frequency divided by 80 equals multiplex rate. For example, a system
clock of 60 kHz gives a multiplex rate of 0.8 kHz.
See Figure 12 for digit select timing diagram.
BCD data output pins — Multiplexed BCD outputs contain three full digits of
information during digit select DS
2
, DS
3
, DS
4
.
During DS
1
, the 1/2 digit, overrange, underrange and polarity information is
available.
Refer to truth table.
Positive power supply — This is the most positive power supply pin.
Not Used.
3
4
5
6
7
CIRCUIT DESCRIPTION
The TC14433 CMOS IC becomes a modified dual-
slope A/D with a minimum of external components. This IC
has the customary CMOS digital logic circuitry, as well as
CMOS analog circuitry. It provides the user with digital
functions (such as counters, latches, multiplexers) and
analog functions (such as operational amplifiers and com-
parators) on a single chip.
Features of this system include auto-zero, high input
impedances and auto-polarity. Low power consumption
and a wide range of power supply voltages are also advan-
tages of this CMOS device. The system's auto-zero function
compensates for the offset voltage of the internal amplifiers
and comparators. In this "ratiometric system," the output
reading is the ratio of the unknown voltage to the reference
voltage, where a ratio of 1 is equal to the maximum count of
1999. It takes approximately 16,000 clock periods to com-
plete one conversion cycle. Each conversion cycle may be
divided into 6 segments. Figure 7 shows the conversion
cycle in 6 segments for both positive and negative inputs.
Segment 1
— The offset capacitor (C
O
), which com-
pensates for the input offset voltages of the buffer and
integrator amplifiers, is charged during this period. How-
ever, the integrator capacitor is shorted. This segment
requires 4000 clock periods.
Segment 2
— During this segment, the integrator
output decreases to the comparator threshold voltage. At
this time, a number of counts equivalent to the input offset
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voltage of the comparator is stored in the offset latches for
later use in the auto-zero process. The time for this segment
is variable and less than 800 clock periods.
START
TIME
SEGMENT
NUMBER
1
2
3
4
5
6
V
X
TYPICAL
POSITIVE
INPUT
VOLTAGE
V
X
TYPICAL
NEGATIVE
INPUT
VOLTAGE
END
Figure 7. Integrator Waveforms at Pin 6
C
1
BUFFER
–
V
X
R
1
INTEGRATOR
+
–
+
COMPARATOR
+
–
Figure 8. Equivalent Circuit Diagrams of the Analog
Section During Segment 4 of the Timing Cycle
3-131
8
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