300mA CMOS LDO With Shutdown,
ERROR Output, And Bypass
TC1173
Bypass Input
A 470pF capacitor connected from the Bypass input to
ground reduces noise present on the internal reference,
which in turn significantly reduces output noise. If output
noise is not a concern, this input may be left unconnected.
Larger capacitor values may be used, but results in a longer
time period to rated output voltage when power is initially
applied.
Equation 1 can be used in conjunction with Equation 2
to ensure regulator thermal operation is within limits. For
example:
GIVEN:
V
IN
MAX
= 3.0V
±
10%
V
OUT
MIN
= 2.7V
±
0.5%
I
LOADMAX
= 250mA
T
J
MAX
= 125°C
T
A
MAX
= 55°C
JA
= 200°C/W
8-Pin MSOP Package
1. Actual power dissipation
2. Maximum allowable dissipation
Thermal Considerations
Thermal Shutdown
Integrated thermal protection circuitry shuts the regula-
tor off when die temperature exceeds 150°C. The regulator
remains off until the die temperature drops to approximately
140°C.
Power Dissipation
The amount of power the regulator dissipates is prima-
rily a function of input and output voltage, and output current.
The following equation is used to calculate worst case
actual
power dissipation:
P
D
≈
(V
IN
MAX
– V
OUT
MIN
)I
LOAD
MAX
Where:
P
D
=
V
IN
MAX
=
V
OUT
MIN
=
I
LOAD
MAX
=
worst case actual power dissipation
maximum voltage on V
IN
minimum regulator output voltage
maximum output (load) current
Equation 1.
FIND:
Actual power dissipation:
P
D
≈
(V
IN
MAX
- V
OUT
MIN
)I
LOAD
MAX
= [(3.0 x 1.1) - (2.7 x .995)]250 x 10
-3
= 155mW
Maximum allowable power dissipation:
P
D
≈
(T
JMAX
– T
AMAX
)
JA
= (125 – 55)
200
= 350mW
In this example, the TC1173 dissipates a maximum of
only 155mW; far below the allowable limit of 350mW. In a
similar manner, Equation 1 and Equation 2 can be used to
calculate maximum current and/or input voltage limits. For
example, the maximum allowable V
IN
is found by substitut-
ing the maximum allowable power dissipation of 350mW
into Equation 1, from which V
IN
MAX
= 4.1V.
Layout Considerations
The primary path of heat conduction out of the package
is via the package leads. Therefore, layouts having a ground
plane, wide traces at the pads, and wide power supply bus
lines combine to lower
JA
and, therefore, increase the
maximum allowable power dissipation limit.
The maximum
allowable
power dissipation (Equation 2)
is a function of the maximum ambient temperature (T
A
MAX
),
the maximum allowable die temperature (125°C), and the
thermal resistance from junction-to-air (
JA
). The 8-Pin
SOIC package has a
JA
of approximately
160
°
C/Watt,
while the 8-Pin MSOP package has a
JA
of approximately
200
°
C/Watt
; both when mounted on a single layer FR4
dielectric copper clad PC board.
P
DMAX
= (T
JMAX
– T
AMAX
)
JA
Where all terms are previously defined.
Equation 2.
TC1173-2
2/2/00
4
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