50mA CMOS LDO WITH SHUTDOWN,
ERROR OUTPUT AND V
REF
BYPASS
PRELIMINARY INFORMATION
TC1072
The following equation is used to calculate worst case
actual
power dissipation:
P
D
≈
(V
INMAX
– V
OUTMIN
)I
LOADMAX
Where:
P
D
V
INMAX
V
OUTMIN
I
LOADMAX
= Worst case actual power dissipation
= Maximum voltage on V
IN
= Minimum regulator output voltage
= Maximum output (load) current
Equation 1.
= (125 – 55)
220
= 318mW
In this example, the TC1072 dissipates a maximum of
only 60mW; far below the allowable limit of 318mW. In a
similar manner, Equation 1 and Equation 2 can be used to
calculate maximum current and/or input voltage limits.
Layout Considerations
The primary path of heat conduction out of the package
is via the package leads. Therefore, layouts having a
ground plane, wide traces at the pads, and wide power
supply bus lines combine to lower
θ
JA
and therefore in-
crease the maximum allowable power dissipation limit.
The maximum
allowable
power dissipation (Equation 2)
is a function of the maximum ambient temperature (T
AMAX
),
the maximum allowable die temperature (125°C) and the
thermal resistance from junction-to-air (θ
JA
). SOT-23A-6
packag has a
θ
JA
of approximately
220
°
C/Watt
when
mounted on a single layer FR4 dielectric copper clad PC
board.
P
D MAX
= (T
JMAX
– T
AMAX)
θ
JA
Where all terms are previously defined.
Equation 2.
Equation 1 can be used in conjunction with Equation 2
to ensure regulator thermal operation is within limits. For
example:
Given:
V
INMAX
= 3.0V
±10%
V
OUTMIN
= 2.7V
±0.5V
I
LOAD
= 40mA
T
AMAX
= 55°C
1. Actual power dissipation
2. Maximum allowable dissipation
Find:
Actual power dissipation:
P
D
≈
(V
INMAX
– V
OUTMIN
)I
LOADMAX
= [(3.0 x 1.05) – (2.7 x .995)]40 x 10
–3
= 18.5mW
Maximum allowable power dissipation:
P
DMAX
= (T
JMAX
– T
AMAX
)
θ
JA
TC1072-01
6/16/97
5
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