73M2901/3.3V
Advanced Single
Chip Modem
RESET
ASYNCHRONOUS AND SYNCHRONOUS SERIAL
DATA INTERFACE
A reset is accomplished by holding the RESET pin
high. To ensure a proper power-on reset, the reset
pin must be held high for a minimum of 3µs. At
power on, the voltage at VPD, VPA, and RESET
must come up at the same time for a proper reset.
The serial data interface consists of the TXD and
RXD data paths (LSBit shifted in and out first,
respectively); and the TXCLK and RXCLK serial
clock outputs associated with the data pins;
CTS/RTS flow control; DCR, DSR and DTR. In
synchronous mode, the data is passed at the bit rate
(tolerance is +1%, -2.5%).
PIN DESCRIPTIONS
POWER PIN DESCRIPTION
PIN NAME
VPA
VNA
32-PIN 44-PIN TYPE DESCRIPTION
15
21
16
22
I
I
I
Positive analog voltage (+ Analog Supply)
Negative analog voltage. (Analog Ground)
Positive digital voltage (+ Digital Supply)
VPD
6, 25,
2,12,
29
27, 33
VND
5, 22, 11, 24,
I
Negative digital voltage. (Digital Ground)
26 44, 28
ANALOG INTERFACE PIN DESCRIPTION
PIN NAME
RXA
TXAN
TXAP
HBDEN
32-PIN 44-PIN TYPE DESCRIPTION
20
16
17
14
21
17
18
15
I
Receive analog data
Transmit Analog -
Transmit Analog +
O
O
I
2w/4w hybrid driver enable pin
0 = Driver configured for 50kΩ or greater load (Tie to VND)
1 = Driver configured for driving line-coupling transformer (Tie to
VPD)
VBG
VREF
19
18
20
19
O
O
Analog Band Gap voltage reference pin (0.1µF to VNA)
Analog reference voltage pin (0.1µF to VNA)
EXTERNAL INTERRUPTS PIN DESCRIPTIONS
PIN NAME
RING
ASRCH
DTR
32-PIN 44-PIN TYPE DESCRIPTION
2
1
39
38
37
I
I
I
External interrupt – Line interface ring detection circuitry input
External interrupt – Autobaud detection, connected to TXD
External interrupt – DTE DTR signal input
32
3
TDK [ TDK ELECTRONICS ]
