Features
1
XIO2000A Features
D
D
Full x1 PCI Express Throughput
D
D
D
Two Package Options: 15 mm x 15 mm and
12 mm x 12 mm
Fully Compliant with PCI Express to
PCI/PCI-X Bridge Specification,
Revision 1.0
Internal PCI Arbiter Supporting Up to 6
External PCI Masters
D
D
D
Fully Compliant with PCI Express Base
Specification, Revision 1.0a
Advanced VC Arbitration Options Include
VC1 Strict Priority, Hardware-Fixed
Round-Robin, and 32-Phase, Weighted
Round-Robin
Fully Compliant with PCI Local Bus
Specification, Revision 2.3
D
Advanced PCI Bus Port Arbitration Options
Include 128-phase, Weighted Round-Robin
Time-Based and 128-phase, Weighted
Round-Robin Aggressive Time-Based
Extended Virtual Channel (VC) Support
Includes a Second VC for
Quality-of-Service and Isochronous
Applications
D
D
Advanced PCI Isochronous Windows for
Memory Space Mapping to a Specified
Traffic Class
D
PCI Express Advanced Error Reporting
Capability Including ECRC Support
D
Support for D1, D2, D3 , and D3
hot
cold
Advanced PCI Express Message Signaled
Interrupt Generation for Serial IRQ
Interrupts from CardBus Applications
D
Active State Link Power Management
Saves Power When Packet Activity on the
PCI Express Link is Idle, Using Both L0s
and L1 States
D
D
D
D
D
D
D
D
External PCI Bus Arbiter Option
PCI Bus LOCK Support
D
D
D
Wake Event and Beacon Support
Clock Run and Power Override Support
Error Forwarding Including PCI Express
Data Poisoning and PCI Bus Parity Errors
Six Buffered PCI Clock Outputs (33 MHz or
66 MHz)
Utilizes 100-MHz Differential PCI Express
Common Reference Clock or 125-MHz
Single-Ended, Reference Clock
PCI Bus Interface 3.3-V and 5.0-V (33 MHz
only at 5.0 V) Tolerance Options
D
D
D
Robust Pipeline Architecture To Minimize
Transaction Latency
Integrated AUX Power Switch Drains V
AUX
Power Only When Main Power Is Off
Full PCI Local Bus 66-MHz/32-Bit
Throughput
Eight 3.3-V, Multifunction, General-Purpose
I/O Terminals
Support for Six Subordinate PCI Bus
Masters with Internal Configurable, 2-Level
Prioritization Scheme
Memory-Mapped EEPROM Serial-Bus
Controller Supporting PCI Express Power
Budget/Limit Extensions for Add-In Cards
D
D
Low Power Design (<350 mW) Ensures
Ease of Implementation
D
Compact Footprint, 201-Ball, GZZ
TM
MicroStar
BGA (XIO2000A only),
TM
Lead-Free 201-Ball, ZZZ MicroStar
175-Ball ZHC MicroStar BGA; or 175-Ball
ZHH MicroStar BGA
BGA;
XIO2000AI Supports Industrial
Temperatures at 33-MHz Bus Speeds
Table 1−1.
Figure 1−1.
MicroStar BGA is a trademark of Texas Instruments.
Other trademarks are the property of their respective owners.
1
April 2007 Revised October 2008
SCPS155C
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
