TSL2560, TSL2561
LIGHT-TO-DIGITAL CONVERTER
TAOS059K
−
APRIL 2007
PARAMETER MEASUREMENT INFORMATION
t
(LOW)
t
(R)
t
(F)
SCL
V
IH
V
IL
t
(HDSTA)
t
(BUF)
t
(HDDAT)
V
IH
V
IL
t
(HIGH)
t
(SUSTA)
t
(SUDAT)
t
(SUSTO)
SDA
P
Stop
Condition
S
Start
Condition
Start
S
Stop
t
(LOWSEXT)
SCL
ACK
SCL
ACK
t
(LOWMEXT)
t
(LOWMEXT)
t
(LOWMEXT)
P
SCL
SDA
Figure 1. Timing Diagrams
1
SCL
9
1
9
SDA
Start by
Master
A6
A5
A4
A3
A2
A1
A0
R/W
ACK by
TSL256x
D7
D6
D5
D4
D3
D2
D1
D0
ACK by Stop by
TSL256x Master
Frame 1 SMBus Slave Address Byte
Frame 2 Command Byte
Figure 2. Example Timing Diagram for SMBus Send Byte Format
1
SCL
9
1
9
SDA
Start by
Master
A6
A5
A4
A3
A2
A1
A0
R/W
ACK by
TSL256x
D7
D6
D5
D4
D3
D2
D1
D0
NACK by Stop by
Master Master
Frame 1 SMBus Slave Address Byte
Frame 2 Data Byte From TSL256x
Figure 3. Example Timing Diagram for SMBus Receive Byte Format
The
LUMENOLOGY
r
Company
r
r
Copyright
E
2007, TAOS Inc.
www.taosinc.com
7
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
