DS90UB913Q, DS90UB914Q
SNLS420B –JULY 2012–REVISED APRIL 2013
www.ti.com
Figure 46 shows a typical connection of the DS90UB914Q Deserializer.
DS90UB914Q (Des)
1.8V
VDDIO
VDDD
VDDIO1
VDDIO2
VDDIO3
C3
C11
C8
C16
C18
VDDR
C9
C4
C5
C12
C13
VDDSSCG
VDDPLL
VDDCML
C10
1.8V
1.8V
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
C14
C17
C19
C6
FB1
FB2
C15
C1
C7
LVCMOS
Parallel
Outputs
ROUT7
ROUT8
ROUT9
ROUT10
ROUT11
HS
RIN1+
RIN1-
Serial
FPD-Link II
Interface
C2
C1
RIN0+
RIN0-
VS
PCLK
C2
LOCK
PASS
1.8V
1.8V
GPIO[0]
GPIO[1]
GPIO[2]
10 kW
10 kW
GPIO[3]
MODE
IDx[0]
RMODE
RID0
PDB
SEL
OEN
1.8V
OSS_SEL
BISTEN
VDDIO
RPU
10 kW
IDx[1]
RPU
C21
RID1
I2C
SCL
SDA
Bus
FB3
NOTE:
Interface
C1 - C2 = 0.1 mF (50 WV)
C3 - C10 = 0.01 mF
FB4
C20
C11 - C16 = 0.1 mF
Optional
C17 - C18 = 4.7 mF
C19 = 22 mF
C20 - C21 = >100 pF
RPU = 1 kW to 4.7 kW
Optional
RES_PIN43
DAP (GND)
RID (see ID[x] Resistor Value Table)
FB1 - FB4: Impedance = 1 kW (@ 100 MHz)
low DC resistance (<1W)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
Figure 46. DS90UB914Q Typical Connection Diagram — Pin Control
54
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