CD54HC670, CD74HC670, CD74HCT670
Functional Diagram
15
1
10
9
Q0
Q1
Q2
Q3
D0
D1
2
7
D2
3
D3
6
12
11
WE
RE
4
5
14
13
RA1
RA0
WA0
WA1
WRITE MODE SELECT TABLE
INPUTS
READ MODE SELECT TABLE
INPUTS
INTERNAL
LATCHES
(NOTE 1)
OPERATING
MODE
INTERNAL
LATCHES
WE
L
D
N
OPERATING
MODE
OUTPUT
Write Data
L
L
H
RE
L
(NOTE 2)
Q
N
L
H
X
Read
L
H
X
L
Data Latched
NOTE:
H
No Change
L
H
Disabled
NOTE:
H
(Z)
1. The Write Address (WA0 and WA1) to the “internal latches” must
be stable while WE is LOW for conventional operation.
2. The selection of the “internal latches” by Read Address (RA0 and
RA1) are not constrained by WE or RE operation.
H = High Voltage Level
L = Low Voltage Level
X= Don’t Care
Z = High Impedance “Off” State
2
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
