C2510Fx / CC2511Fx
13.15 I2S
Please see Section 13.4.6.6 for details on I/O
pin mapping for the I2S interface. When the
module is in master mode, it drives the SCK
and WS lines. When the I2S interface is in slave
mode, these lines are driven by an external
master. The data on the serial data lines is
transferred one bit per SCK cycle, most
significant bit first. The WS signal selects the
channel of the current word transfer (left = 0,
right = 1). It also determines the length of each
word. There is a transition on the WS line one
bit time before the first word is transferred and
before the last bit of each word. Figure 41
shows the I2S signaling. Only a single serial
data signal is shown in this figure. The SD
signal could be the RX or TX signal depending
on the direction of the data.
The CC2510Fx/CC2511Fx provides an industry
standard I2S interface. The I2S interface can be
used to transfer digital audio samples between
the CC2510Fx/CC2511Fx and an external audio
device.
The I2S interface can be configured to operate
as master or slave and may use mono as well
as stereo samples. When mono mode is
enabled, the same audio sample will be used
for both channels. Both full and half duplex is
supported and automatic µ-Law compression
and expansion can be used.
The I2S interface consists of 4 signals:
• Continuous Serial Clock (SCK)
• Word Select (WS)
• Serial Data In (RX)
• Serial Data Out (TX)
SCK
WS
MSB
LSB
MSB
LSB
MSB
SD
SAMPLE n,
SAMPLE n+1,
SAMPLE n-1,
LEFT CHANNEL
RIGHT CHANNEL
RIGHT CHANNEL
Figure 41: I2S Digital Audio Signaling
• I2S RX: I2SCFG0.RXIEN
• I2S TX: I2SCFG0.TXIEN
Interrupt flags:
13.15.1
Enabling I2S
The I2SCFG0.ENAB bit must be set to 1 to
enable the I2S transmitter/receiver. However,
when I2SCFG0.ENAB is 0, the I2S can still be
• I2S RX: I2SSTAT.RXIRQ
• I2S TX: I2SSTAT.TXIRQ
used
as
a
stand-alone
µ-Law
compression/expansion engine. Refer to
Section 13.15.12 on Page 166 for more details
about this.
The TX interrupt flag I2SSTAT.TXIRQ is
asserted together with IRCON2.I2STXIF
when the internal TX buffer is empty and the
I2S fetches the new data previously written to
the I2SDATH:I2SDATL registers. The TX
interrupt flag, I2SSTAT.TXIRQ, is cleared
when I2SDATHregister is written. An interrupt
13.15.2
The I2S has two interrupts:
I2S Interrupts
• I2S RX complete interrupt (I2SRX)
• I2S TX complete interrupt (I2STX)
The I2S interrupt enable bits are found in the
I2SCFG0 register. The interrupt flags are
located in the I2SSTAT register. The interrupt
enables and flags are summarized below.
request
is
only
generated
when
I2SCFG0.TXIEN and IEN2.I2STXIE are
both set to 1.
The RX interrupt flag I2SSTAT.RXIRQ is
asserted together with TCON.I2SRXIF when
the internal RX buffer is full and the contents of
Interrupt enable bits:
SWRS055D
Page 163 of 243
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