C2510Fx / CC2511Fx
13.9 8-bit Timers, Timer 3 and Timer 4
Timer 3 and Timer 4 are two 8-bit timers which
supports typical timer/counter functions such
as output compare and PWM functions. The
timers have two independent compare
channels each and use one I/O pin per
channel.
speed RC oscillator is used as system clock
source, the highest clock frequency used by
Timer 3/4 is fXOSC/2 for CC2510Fx and 12 MHz
for CC2511Fx, given that the HS RCOSC has
been calibrated.
The counter operates as either a free-running
counter, a modulo counter, a down counter, or
as an up/down counter for use in centre-
aligned PWM.
The features of Timer 3/4 are as follows:
• Two compare channels
• Set, clear, or toggle output compare
It is possible to read the 8-bit counter value
through the SFR TxCNT.
• Free-running,
modulo,
up/down counter operation
down,
or
Writing a 1 to TxCTL.CLR will reset the 8-bit
• Clock prescaler for divide by 1, 2, 4, 8,
counter.
16, 32, 64, 128
The counter may produce an interrupt request
when the terminal count value (overflow) is
reached (see Section 13.9.2.1 – Section
13.9.2.4). It is possible to start and halt the
counter with the TxCTL.START bit. The
counter is started when a 1 is written to
• Interrupt request generation on compare
and when reaching the terminal count
value
• DMA trigger function
TxCTL.START. If
TxCTL.START, the counter halts at its
present value.
a
0
is written to
Note: In the following sections, an n in the
register name represent the channel
number 0 or 1 if nothing else is stated. An
x in the register name refers to the timer
number, 3 or 4
13.9.2 Timer 3/4 Operation
In general, the control register TxCTL is used
to control the timer operation. The timer
modes are described in the following four
sections.
13.9.1 8-bit Timer Counter
Both timers consist of an 8-bit counter that
increments or decrements at each active clock
edge. The frequency of the active clock edges
13.9.2.1 Free-running Mode
is
given
by
CLKCON.TICKSPD
and
In free-running mode the counter starts from
0x00 and increments at each active clock
edge. When the counter reaches the terminal
count value 0xFF (overflow), the counter is
loaded with 0x00 and continues incrementing
its value as shown in Figure 34. When 0xFF is
reached, the TIMIF.TxOVFIF flag is set. The
IRCON.TxIF flag is only asserted if the
TxCTL.DIV. CLKCON.TICKSPDis used to set
the timer tick speed. The timer tick speed will
vary from 203.125 kHz to 26 MHz for CC2510Fx
and 187.5 kHz to 24 MHz for CC2511Fx (given
the use of a 26 MHz or 48 MHz crystal
respectively). Note that the clock speed of the
system clock is not affected by the TICKSPD
setting. The timer tick speed is further divided
in Timer 3/4 by the prescaler value set by
TxCTL.DIV. This prescaler value can be 1,
2, 4, 8, 16, 32, 64, or 128. Thus the lowest
clock frequency used by Timer 3/4 is 1.587
kHz and the highest is 26 MHz when a 26
MHz crystal oscillator is used as system clock
source (CC2510Fx). The lowest clock frequency
used by Timer 3/4 is 1.465 kHz and the
highest is 24 MHz for CC2511Fx. When the high
corresponding
interrupt
mask
bit
TxCTL.OVFIM is set. An interrupt request is
generated when both TxCTL.OVFIM and
IEN1.TxEN are set to 1. The free-running
mode can be used to generate independent
time intervals and output signal frequencies.
SWRS055D
Page 129 of 243
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