C2510Fx / CC2511Fx
instruction cycles to access, thus giving slow
access. XDATA assesses is also slower in
hardware than DATA accesses as the CODE
and XDATA memory spaces share a common
bus on the CPU core (instruction pre-fetch
from CODE can not be performed in parallel
with XDATA accesses).
11.2.1 Memory Map
This section gives an overview of the memory
map.
Both the DATA and the SFR memory space is
mapped to the XDATA and CODE memory
space as shown in Figure 14, Figure 15, and
Figure 16 (the CODE and XDATA memory
spaces are mapped identically), and
CC2510FX/CC2511FX has what can be called a
unified memory space.
SFR. A 7-bit read/write register memory
space, which can be directly accessed by a
single CPU instruction. For SFRs whose
address is divisible by eight, each bit is also
individually addressable.
Mapping all the memory spaces to XDATA
allows the DMA controller access to all
physical memory and thus allows DMA
transfers between the different 8051 memory
spaces. This also means that any instruction
that read, write, or manipulate an XDATA
variable can be used on the entire unified
memory space, except writing to or changing
data in flash.
The four different memory spaces are distinct
in the 8051 architecture, but are partly
overlapping in the CC2510Fx/CC2511Fx to ease
DMA transfers and hardware debugger
operation.
How the different memory spaces are mapped
onto the three physical memories (8/16/32 KB
flash program memory, 1/2/48 KB SRAM, and
hardware registers (SFR, radio, I2S, and USB
(CC2511Fx)) is described in Section 11.2.1 and
Section 11.2.2.
Mapping all memory spaces to the CODE
memory space is primarily done to allow
program execution out of the SRAM/XDATA.
SWRS055D
Page 39 of 243
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