C2510Fx / CC2511Fx
Byte
Bit
Field Name
Description
Offset
7
5:4
DESTINC[1:0]
Destination address increment mode (after each transfer)
00
01
10
11
0 bytes/words
1 bytes/words
2 bytes/words
-1 bytes/words
7
7
3
2
IRQMASK
M8
Interrupt Mask for this channel.
0
1
Disable interrupt generation
Enable interrupt generation upon DMA channel done
Mode of 8th bit in transfer count for variable length transfers (VLEN≠000and
VLEN≠111). Only applicable when WORDSIZE=0.
0
1
Use all 8 bits for transfer count
Use 7 LSB for transfer count
7
1:0
PRIORITY[1:0]
The DMA channel priority:
00
01
Low, DMA access will always defer to a CPU access
Normal, guarantees that DMA access prevails over CPU on at least every
second try.
10
11
High, DMA access will always prevail over CPU access.
Reserved
Table 52: DMA Configuration Data Structure
SWRS055D
Page 107 of 243
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
