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CC2430F32RTC 参数 Datasheet PDF下载

CC2430F32RTC图片预览
型号: CC2430F32RTC
PDF下载: 下载PDF文件 查看货源
内容描述: 真正的系统级芯片解决方案的2.4 GHz IEEE 802.15.4 / ZigBee的 [A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee]
分类和应用: 电信集成电路
文件页数/大小: 212 页 / 1862 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
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CC2430  
Peripherals : AES Coprocessor  
13.12 AES Coprocessor  
The CC2430 data encryption is performed using  
a dedicated coprocessor which supports the  
Advanced Encryption Standard, AES. The  
coprocessor allows encryption/decryption to be  
performed with minimal CPU usage.  
Supports all security suites in IEEE  
802.15.4  
ECB, CBC, CFB, OFB, CTR and CBC-  
MAC modes.  
Hardware support for CCM mode  
128-bits key and IV/Nonce  
DMA transfer trigger capability  
The coprocessor has the following features:  
13.12.1 AES Operation  
To encrypt a message, the following procedure  
must be followed (ECB, CBC):  
The AES coprocessor works on blocks of 128  
bits. A block of data is loaded into the  
coprocessor, encryption is performed and the  
result must be read out before the next block  
can be processed. Before each block load, a  
dedicated start command must be sent to the  
coprocessor.  
Load key  
Load initialization vector (IV)  
Download  
encryption/decryption.  
and  
upload  
data  
for  
13.12.2 Key and IV  
Before a key or IV/nonce load starts, an  
appropriate load key or IV/nonce command  
must be issued to the coprocessor. When  
loading the IV it is important to also set the  
correct mode.  
The key, once loaded, stays valid until a key  
reload takes place.  
The IV must be downloaded before the  
beginning of each message (not block).  
Both key and IV values are cleared by a reset  
of the device.  
A key load or IV load operation aborts any  
processing that could be running.  
13.12.3 Padding of input data  
The AES coprocessor works on blocks of 128  
bits. If the last block contains less than 128  
bits, it must be padded with zeros when written  
to the coprocessor.  
13.12.4 Interface to CPU  
The CPU communicates with the coprocessor  
using three SFR registers:  
When using DMA with AES coprosessor, two  
DMA channels must be used, one for input  
data and one for output data. The DMA  
channels must be initialized before a start  
command is written to the ENCCS. Writing a  
start command generates a DMA trigger and  
the transfer is started. After each block is  
processed, an interrupt is generated. The  
interrupt is used to issue a new start command  
to the ENCCS.  
ENCCS, Encryption control and status  
register  
ENCDI, Encryption input register  
ENCDO, Encryption output register  
Read/write to the status register is done  
directly by the CPU, while access to the  
input/output registers should be performed  
using direct memory access (DMA).  
13.12.5 Modes of operation  
When using CFB, OFB and CTR mode, the  
128 bits blocks are divided into four 32 bit  
blocks. 32 bits are loaded into the AES  
coprocessor and the resulting 32 bits are read  
out. This continues until all 128 bits have been  
encrypted. The only time one has to consider  
this is if data is loaded/read directly using the  
CPU. When using DMA, this is handled  
automatically by the DMA triggers generated  
by the AES coprocessor, thus DMA is  
preferred.  
Both encryption and decryption are performed  
similarly.  
The CBC-MAC mode is a variant of the CBC  
mode. When performing CBC-MAC, data is  
downloaded to the coprocessor one 128 bits  
block at a time, except for the last block.  
Before the last block is loaded, the mode must  
CC2430 Data Sheet (rev. 2.1) SWRS036F  
Page 136 of 211