CC2430
Peripherals : Sleep Timer
13.9 Sleep Timer
The Sleep timer is used to set the period
between when the system enters and exits
low-power sleep modes.
The main features of the Sleep timer are the
following:
•
24-bit timer up-counter operating at 32kHz
clock
The Sleep timer is also used to maintain timing
in Timer 2 (MAC Timer) when entering a low-
power sleep mode.
•
•
•
24-bit compare
Low-power mode operation in PM2
Interrupt and DMA trigger
13.9.1
Timer Operation
This section describes the operation of the
timer.
13.9.1.1
General
The Sleep timer is a 24-bit timer running on
the 32kHz clock (either RC or XOSC). The
timer starts running immediately after a reset
and continues to run uninterrupted. The
current value of the timer can be read from the
SFR registers ST2:ST1:ST0.
13.9.1.2
Timer Compare
A timer compare occurs when the timer value
is equal to the 24-bit compare value. The
compare value is set by writing to the registers
ST2:ST1:ST0. When a timer compare occurs
the interrupt flag STIF is asserted.
used to wake up the device and return to
active operation in PM0.
The default value of the compare value after
reset is 0xFFFFFF. Note that before entering
PM2 one should wait for ST0 to change after
setting new compare value.
The interrupt enable bit for the ST interrupt is
IEN0.STIE
IRCON.STIF.
and the interrupt flag is
The Sleep timer compare can also be used as
a DMA trigger (DMA trigger 11 in Table 41).
When operating in all power modes except
PM3 the Sleep timer will be running. In PM1
and PM2 the Sleep timer compare event is
Note that if supply voltage drops below 2V
while being in PM2, the sleep interval might be
affected.
13.9.1.3
Sleep Timer Registers
The registers used by the Sleep Timer are:
• ST2– Sleep Timer 2
• ST1– Sleep Timer 1
• ST0– Sleep Timer 0
ST2 (0x97) – Sleep Timer 2
Bit
Name
Reset
R/W
Description
ST2[7:0]
7:0
0x00
R/W
Sleep timer count/compare value. When read, this register returns the
high bits [23:16] of the sleep timer count. When writing this register sets
the high bits [23:16] of the compare value. The value read is latched at
the time of reading register ST0. The value written is latched when ST0
is written.
ST1 (0x96) – Sleep Timer 1
Bit
Name
Reset
R/W
Description
ST1[7:0]
7:0
0x00
R/W
Sleep timer count/compare value. When read, this register returns the
middle bits [15:8] of the sleep timer count. When writing this register
sets the middle bits [15:8] of the compare value. The value read is
latched at the time of reading register ST0. The value written is latched
when ST0is written.
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 126 of 211
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