CC2430
8051 CPU : Interrupts
11.5.2
Interrupt Processing
When an interrupt occurs, the CPU will vector
to the interrupt vector address as shown in
Table 30. Once an interrupt service has
begun, it can be interrupted only by a higher
priority interrupt. The interrupt service is
terminated by a RETI (return from interrupt
instruction). When an RETI is performed, the
CPU will return to the instruction that would
have been next when the interrupt occurred.
instruction cycle the interrupt will be
acknowledged by hardware forcing an LCALL
to the appropriate vector address.
Interrupt response will require a varying
amount of time depending on the state of the
CPU when the interrupt occurs. If the CPU is
performing an interrupt service with equal or
greater priority, the new interrupt will be
pending until it becomes the interrupt with
highest priority. In other cases, the response
time depends on current instruction. The
fastest possible response to an interrupt is
seven machine cycles. This includes one
machine cycle for detecting the interrupt and
When the interrupt condition occurs, the CPU
will also indicate this by setting an interrupt
flag bit in the interrupt flag registers. This bit is
set regardless of whether the interrupt is
enabled or disabled. If the interrupt is enabled
when an interrupt flag is set, then on the next
six cycles to perform the LCALL
.
TCON (0x88) – Interrupt Flags
Bit
Name
Reset
R/W
Description
7
0
R/W
H0
URX1IF – USART1 RX interrupt flag. Set to 1 when USART1 RX
interrupt occurs and cleared when CPU vectors to the interrupt
service routine.
URX1IF
0
1
Interrupt not pending
Interrupt pending
6
5
0
0
R/W
Not used
-
R/W
H0
ADCIF – ADC interrupt flag. Set to 1 when ADC interrupt occurs
and cleared when CPU vectors to the interrupt service routine.
ADCIF
0
1
Interrupt not pending
Interrupt pending
4
3
0
0
R/W
Not used
-
R/W
H0
URX0IF – USART0 RX interrupt flag. Set to 1 when USART0
interrupt occurs and cleared when CPU vectors to the interrupt
service routine.
URX0IF
0
1
Interrupt not pending
Interrupt pending
2
1
1
0
R/W
Reserved. Must always be set to 1. Setting a zero will enable low
level interrupt detection, which is almost always the case (one-shot
when interrupt request is initiated)
IT1
R/W
H0
RFERRIF – RF TX/RX FIFO interrupt flag. Set to 1 when RFERR
interrupt occurs and cleared when CPU vectors to the interrupt
service routine.
RFERRIF
0
1
Interrupt not pending
Interrupt pending
0
1
R/W
Reserved. Must always be set to 1. Setting a zero will enable low
level interrupt detection, which is almost always the case (one-shot
when interrupt request is initiated)
IT0
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 54 of 211
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