CC2430
Debug Interface : Debug Mode
12 Debug Interface
The debug interface uses the I/O pins P2_1 as
Debug Data and P2_2 as Debug Clock during
Debug mode. These I/O pins can be used as
general purpose I/O only while the device is
not in Debug mode. Thus the debug interface
does not interfere with any peripheral I/O pins.
The CC2430 includes a debug interface that
provides a two-wire interface to an on-chip
debug module. The debug interface allows
programming of the on-chip flash and it
provides access to memory and registers
contents and debug features such as
breakpoints, single-stepping and register
modification.
12.1 Debug Mode
Debug mode is entered by forcing two rising
edge transitions on pin P2_2 (Debug Clock)
while the RESET_N input is held low.
While in Debug mode pin P2_1 is the Debug
Data bi-directional pin and P2_2 is the Debug
Clock input pin.
12.2 Debug Communication
The debug interface uses an SPI-like two-wire
interface consisting of the P2_1 (Debug Data)
and P2_2 (Debug Clock) pins. Data is driven
on the bi-directional Debug Data pin at the
positive edge of Debug Clock and data is
sampled on the negative edge of this clock.
shows a timing diagram of data on the debug
interface.
The first byte of the debug command is a
command byte and is encoded as follows:
•
•
bits 7 to 3 : instruction code
bits 2 : return input byte to host
when high
Debug commands are sent by an external host
and consist of 1 to 4 output bytes (including
command byte) from the host and an optional
input byte read by the host. Command and
data is transferred with MSB first. Figure 11
•
bits 1 to 0 : number of bytes from host
following command byte
Figure 11: Debug interface timing diagram
12.3 Debug Commands
The debug commands are shown in Table 35.
Some of the debug commands are described
in further detail in the following sub-sections.
12.4 Debug Lock Bit
For software and/or access protection a set of
lock bits can be written. This information is
contained in the Flash Information page
(section 11.2.3 under Flash memory), at
location 0x000 and the flash information page
can only be accessed through the debug
interface. There are three kinds of lock protect
bits as described in this section.
page (page 0 ranging from address 0 to
0x07FF). When BBLOCK is set to 0, the boot
sector page is locked.
The third type of lock protect bit is DBGLOCK,
which is used to disable hardware debug
support through the Debug Interface. When
DBGLOCK is set to 0, almost all debug
commands are disabled.
The LSIZE[2:0]lock protect bits are used to
define a section of the flash memory which is
write protected. The size of the write protected
area can be set by the LSIZE[2:0] lock bits
in sizes of eight steps from 0 to 128 KB (all
starting from top of flash memory and defining
a section below this).
When the Debug Lock bit, DBGLOCKis set to 0
(see Table 34) all debug commands except
CHIP_ERASE,
READ_STATUS
and
GET_CHIP_ID are disabled and will not
function. The status of the Debug Lock bit can
be read using the READ_STATUS command
(see section 12.4.2).
The second type of lock protect bits is
BBLOCK, which is used to lock the boot sector
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 60 of 211
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
