CC1110Fx / CC1111Fx
Bit
7:5
4
Name
Description
Reserved, write as 0
Boot Block Lock
BBLOCK
0
1
Page 0 is write protected
Page 0 is writeable, unless LSIZE is 000
3:1
LSIZE[2:0]
Lock Size. Sets the size of the upper flash area which is write-protected. Byte
sizes are listed below
000 32 KB (all pages)
001 24 KB
010 16 KB
011 8 KB
CC1110F32 and CC1111F32 only
CC1110F32 and CC1111F32 only
CC1110F32 and CC1111F32 only
CC1110F32 and CC1111F32 only
CC1110F32 and CC1111F32 only
CC1110F32 and CC1111F32 only
100 4 KB
101 2 KB
110 1 KB
111 0 bytes (no pages)
Debug lock bit
0
DBGLOCK
0
1
Disable debug commands
Enable debug commands
Table 44: Flash Lock Protection Bits Definition
12.4 Debug Commands
The debug commands are shown in Table 45.
Some of the debug commands are described
in further detail in the following sections
with the breakpoint. When a match occurs, the
CPU is halted.
When issuing the SET_HW_BRKPNT debug
command, the external host must supply three
data bytes that define the hardware
breakpoint. The hardware breakpoint itself
consists of 18 bits while three bits are used for
control purposes. The format of the three data
bytes for the SET_HW_BRKPNT command is
as follows.
12.4.1 Debug Configuration
The
commands
WR_CONFIG
and
RD_CONFIG are used to access the debug
configuration data byte. The format and
description of this configuration data is shown
in Table 46
The first data byte consists of the following:
12.4.2 Debug Status
Bit Description
A debug status byte is read using the
READ_STATUS command. The format and
description of this debug status is shown in
Table 47.
7:5 Unused
4:3 Breakpoint number; 0 - 3
2
Breakpoint enable
The READ_STATUS command is used e.g.
for polling the status of flash chip erase after a
CHIP_ERASE command or oscillator stable
status required for debug commands HALT,
RESUME, DEBUG_INSTR, STEP_REPLACE,
and STEP_INSTR.
0
1
Disable
Enable
1:0 Reserved. Must be 00.
The second data byte consists of bits 15 - 8 of
the hardware breakpoint while the third data
byte consists of bits 7-0 of the hardware
breakpoint. This means that the second and
third data byte sets the CPU CODE address
where the CPU is halted.
12.4.3 Hardware Breakpoints
The debug command SET_HW_BRKPNT is
used to set a hardware breakpoint. The
CC1110Fx/CC1111Fx supports up to four hardware
breakpoints. When a hardware breakpoint is
enabled it will compare the CPU address bus
SWRS033E
Page 73 of 239
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