CC1110Fx / CC1111Fx
Periphery /
Function
P0
P1
7
P2
712
612
5
4
3
2
1
0
6
5
4
3
2
1
0
4
3
2
1
0
ADC
A7
A6
A5
C
A4
SS
A3
M0
A2
MI
A1
A0
USART0 Alt. 1
SPI
Alt. 2
MO
TX
C
MI
C
SS
CT
USART0 Alt. 1
UART Alt. 2
USART1 Alt. 1
RT
MI
CT
M0
TX
2
TX
C
RX
SS
CT
0
RX
SS
CT
RT
SPI
Alt. 2
MI
M0
TX
USART1 Alt. 1
UART Alt. 2
TIMER1 Alt. 1
Alt. 2
RX
RT
1
RX
RT
0
1
1
2
0
TIMER3 Alt. 1
Alt. 2
1
0
1
0
TIMER4 Alt. 1
Alt. 2
1
0
I2S
Alt. 1
Alt. 2
CK
WS
RX
TX
CK
Q1
WS
DC
RX
DD
TX
32.768 kHz
XOSC
Q2
DEBUG
Table 50: Peripheral I/O Pin Mapping
12 This pin is only found on CC1110Fx ,it does not exist on CC1111Fx.
13.4.6.1 USART0
that if USART0 is configured to operate in
UART mode with hardware flow control
disabled, USART1 or timer 1 will have
precedence to use ports P0_4 and P0_5. It is
the user’s responsibility to not assign more
than two peripherals to the same pin locations,
as P2DIR.PRIP0 will not give a conclusive
order of precedence if more than two
peripherals are in conflict on a pin.
The SFR bit PERCFG.U0CFG selects whether
to use alternative 1 or alternative 2 locations.
In Table 50, the USART0 signals are shown
as follows:
SPI:
• SCK: C
• SSN: SS13
• MOSI: MO
• MISO: MI
P2SEL.PRI3P1,
P2SEL.PRI2P1,
P2SEL.PRI1P1, and P2SEL.PRI0P1 select
the order of precedence when assigning two,
and in some cases three, peripherals to P1.
An example is if both the USARTs are assign
to P1 together with Timer 1 (channel 2, 1, and
0). By setting both PRI3P1 and PRI0P1 to 0,
USART0 will have precedence. Note that if
USART0 is configured to operate in UART
mode with hardware flow control disabled,
USART1 can still use P1_7 and P1_6, while
Timer 1 can use P1_2, P1_1, and P1_0. Also
on P1 it is the user’s responsibility to make
sure that there is a conclusive order of
precedence based on the PERCFGand P2SEL
settings.
UART:
• RXDATA: RX
• TXDATA: TX
• RTS: RT
• CTS: CT
P2DIR.PRIP0
selects
the
order
of
precedence when assigning two peripherals to
the same pin location on P0. When set to 00,
USART0 has precedence if both USART0 and
USART1 are assigned to the same pins. Note
13
SSN should only be configured as a
pheripheral when using SPI slave mode
SWRS033E
Page 93 of 239
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