CC1110Fx / CC1111Fx
(see Table 11 and Table 12) the HS RCOSC
should be used and HS XOSC should not be
enabled. This applies for all power modes,
except PM0, and only if LS RCOSC is enabled
(CLKCON.OSC32K=1).
possible. The SLEEP.MODE will be cleared to
00 by HW when power mode is entered, thus
interrupts are enabled during power modes. All
interrups not to be used to wake up from PM
modes must be disabled before setting
SLEEP.MODE ≠ 0.
13.1.4 Power Management Registers
It should be noted that after enabling HS
XOSC (CLKCON.OSC=0) one has to ensure
This section describes the Power Management
registers. All register bits retain their previous
values when entering PM2 or PM3 unless
otherwise stated.
that
the
HS
XOSC
is
stable
(SLEEP.XOSC_STB=1) before entering power
mode. If up-time, time in-between power
modes, is shorter than HS XOSC startup time
PCON (0x87) – Power Mode Control
Bit
7:2
1
Name
Reset
R/W
Description
0
0
0
R/W
Not used
R0/W1 Reserved. Must be set to 0. Failure to do so will stop CPU from operating.
0
IDLE
R0/W1
H0
Power mode control. Writing a 1 to this bit forces CC1110Fx/CC1111Fx to enter
the power mode set by SLEEP.MODE. This bit is always read as 0.
All interrupt requests will clear this bit and CC1110Fx/CC1111Fx will reenter active
mode.
Note: see section 13.1.3 for details on how this bit should be used.
SWRS033E
Page 79 of 239
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