CC1110Fx / CC1111Fx
a data packet with payload less than 32 bytes
denotes the end of the transfer.
packet, and a handshake packet17). If more
than 32 bytes (maximum packet size) is to be
sent, the data must be split into a number of 32
byte packets followed by a residual packet. If
the number of bytes to send is a multiple of 32,
the residual packet will be a zero length data
packet, hence a packet size less than 32 bytes
denotes the end of the transfer.
The USBCS0.OUTPKT_RDY bit will be set and
an EP0 interrupt will be generated when a data
packet has been received. The firmware
should set USBCS0.CLR_OUTPKT_RDY when
the data packet has been unloaded from the
EP0 FIFO. When the last data packet has
been received (packet size less than 32 bytes)
Firmware should load the EP0 FIFO with the
first
data
packet
and
set
the
firmware
should
also
set
the
USBCS0.INPKT_RDY bit as soon as possible
after the USBCS0.CLR_OUTPKT_RDY bit has
been set. The USBCS0.INPKT_RDY will be
cleared and an EP0 interrupt will be generated
when the data packet has been sent. Firmware
might then load more data packets as
necessary. An EP0 interrupt will be generated
for each packet sent. Firmware must set
USBCS0.DATA_END bit. This will start the
Status stage of the control transfer. The size of
the data packet is kept in the USBCNT0
registers. Note that this value is only valid
when USBCS0.OUTPKT_RDY=1.
EP0 will switch to the IDLE state when the
Status stage has completed. The Status stage
may fail if the DATA1 packet received is not a
zero length data packet or if the
USBCS0.SEND_STALL bit is set to 1. The
USBCS0.SENT_STALL bit will then be
asserted and an EP0 interrupt will be
generated as explained in section 13.16.5.1.
USBCS0.DATA_END
in
addition
to
USBCS0.INPKT_RDY when the last data
packet has been loaded. This will start the
Status stage of the control transfer.
EP0 will switch to the IDLE state when the
Status stage has completed. The Status stage
may fail if the USBCS0.SEND_STALL bit is set
to 1. The USBCS0.SENT_STALL bit will then
be asserted and an EP0 interrupt will be
generated as explained in section 13.16.5.1.
13.16.6 Endpoints 1 – 5
Each endpoint can be used as an IN only, an
OUT only, or IN/OUT. For an IN/OUT endpoint
there are basically two endpoints, an IN
endpoint and an OUT endpoint associated with
the endpoint number. Configuration and
control of IN endpoints is performed through
the USBCSIL and USBCSIH registers. The
USBCSOL and USBCSOH registers are used to
configure and control OUT endpoints. Each IN
and OUT endpoint can be configured as either
If USBCS0.INPKT_RDY is not set when
receiving an IN token, the USB Controller will
reply with a NAK to indicate that the endpoint
is working, but temporarily has no data to
send.
13.16.5.4 OUT Transactions (RX state)
Isochronous
(USBCSIH.ISO=1
and/or
Bulk/Interrupt
and/or
If the control transfer requires data to be
received from the host, the Setup stage will be
followed by one or more OUT transactions in
the Data stage. In this case the USB controller
will be in RX state and only accept OUT
USBCSOH.ISO=1)
(USBCSIH.ISO=0
USBCSOH.ISO=0)
Interrupt endpoints are handled identically by
the USB controller but will have different
properties from a firmware perspective.
or
endpoints.
Bulk
and
tokens.
A
successful OUT transaction
comprises two or three sequential packets (a
token packet, a data packet, and a handshake
packet18). If more than 32 bytes (maximum
packet size) is to be received, the data must
be split into a number of 32 byte packets
followed by a residual packet. If the number of
bytes to receive is a multiple of 32, the residual
packet will be a zero length data packet, hence
The USBINDEXregister must have the value of
the endpoint number before the Indexed
Endpoint Registers are accessed (see Table
35 on page 53).
13.16.6.1 FIFO Management
Each endpoint has a certain number of FIFO
memory bytes available for incoming and
outgoing data packets. Table 60 shows the
FIFO size for endpoints 1 - 5. It is the firmware
that is responsible for setting the USBMAXIand
USBMAXO registers correctly for each endpoint
to prevent data from being overwritten.
17 For isochronous transfers there would not be
a handshake packet from the host
18 For isochronous transfers there would not be
a handshake packet from the CC1111Fx
SWRS033E
Page 172 of 239
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