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CC1111F32RSP 参数 Datasheet PDF下载

CC1111F32RSP图片预览
型号: CC1111F32RSP
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗低于1 GHz的射频系统级芯片(SoC )与MCU,存储器,收发器和USB控制器 [Low-power sub-1 GHz RF System-on-Chip (SoC) with MCU, memory, transceiver, and USB controller]
分类和应用: 存储射频控制器PC
文件页数/大小: 240 页 / 2823 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
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CC1110Fx / CC1111Fx  
13.12.7 AES DMA Triggers  
DMA channels used to transfer data to or  
from the AES coprocessor.  
There are two DMA triggers associated with  
the AES coprocessor. These are ENC_DW,  
which is active when input data needs to be  
downloaded to the ENCDI register, and  
ENC_UP, which is active when output data  
needs to be uploaded from the ENCDO  
register.  
13.12.8 AES Registers  
The AES coprocessor registers are  
described below. These registers will be in  
their reset state when returning to active  
mode from PM2 and PM3.  
The ENCDI and ENCDO registers should be  
set as destination and source locations for  
ENCCS (0xB3) – Encryption Control and Status  
Bit  
Name  
Reset  
R/W  
Description  
7
0
R0  
Not used  
6:4  
MODE[2:0]  
000  
R/W  
Encryption/decryption mode  
000  
001  
010  
011  
100  
101  
110  
111  
CBC  
CFB  
OFB  
CTR  
ECB  
CBC MAC  
Reserved  
Reserved  
3
RDY  
1
0
R
Encryption/decryption ready status  
0
1
Encryption/decryption in progress  
Encryption/decryption is completed  
2:1  
CMD[1:0]  
R/W  
Command to be performed when a 1 is written to ST.  
00  
01  
10  
11  
encrypt block  
decrypt block  
load key  
load IV/nonce  
0
ST  
0
R/W1  
H0  
Start processing command set by CMD. Must be issued for each command or  
128 bits block of data. Cleared by hardware  
ENCDI (0xB1) – Encryption Input Data  
Bit  
Name  
Reset  
R/W  
Description  
7:0  
DIN[7:0]  
0x00  
R/W  
Encryption input data.  
ENCDO (0xB2) – Encryption Output Data  
Bit  
Name  
Reset  
R/W  
Description  
7:0  
DOUT[7:0]  
0x00  
R/W  
Encryption output data.  
SWRS033E  
Page 150 of 239  
 
 
 
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